IEEE Transactions on Quantum Engineering
Integrated Superconducting High-$Q$ Seamless Cavity for Quantum Memory and Qubit Readout Applications
Mohamed F. Hagag, Kareem H. El‐Gendy, Bashar Zyoud, Thomas R. Jones, Karim G. Seddik, Dimitrios Peroulis
Abstract
This work presents a novel micromachined, seamless sapphire–silicon hybrid evanescent-mode cavity architecture incorporating selectively engineered coupling channels and flux-tunable external coupling via a superconducting quantum interference device (SQUID). The proposed design enables two simulated operating states within a single device: an ultra-high- $Q$ memory configuration and a high-speed readout configuration with intrinsic Purcell filtering, which is expected to enhance readout fidelity while preserving the coherence of the stored quantum information. Unlike prior 3-D and multimode cavity approaches, the design employs a distributed embedded-capacitance network that confines electric fields into ultra-low-loss dielectric regions while distributing magnetic fields to an air-filled enclosure, thus substantially reducing simulated surface and dielectric losses beyond reported architectures. Moreover, the structure employs contactless superconducting metallization between two wafers, eliminating seam losses typically observed in micromachined resonators. The designed selective field-coupling strategy enables pure magnetic coupling through the lower silicon substrate, enabling fast readout, while pure electric coupling through the upper sapphire interface ensures strong qubit–cavity interaction, without mixed-coupling artifacts. High-fidelity mixed electromagnetic and circuit-level modeling predicts an intrinsic- $Q$ exceeding $10^{8}$ at 5554.5 MHz. The flux-tunable asymmetric DC-SQUID enables a dynamic external- $Q$ reconfiguration from $10^{9}$ (memory mode) to $10^{4}$ (readout mode). When coupled to a 6981.7 MHz transmon qubit, the architecture provides a nearly six-order-of-magnitude simulated Purcell-limited qubit lifetime improvement and achieves 66 $\%$ simulated memory efficiency at 1 ms under realistic coherence assumptions. These simulated results show that the proposed seamless, capacitively engineered architecture can work as a promising, high-coherence, and rapidly reconfigurable platform for scalable superconducting quantum systems.