This study introduces a superconducting quantum chip architecture designed to simultaneously preserve entanglement and readout fidelity, addressing one of the key trade-offs in the development of scalable quantum hardware. In conventional quantum circuits, strong qubit qubit coupling enhances entanglement but often leads to undesired crosstalk, dephasing, and reduced measurement fidelity. To mitigate these effects, we propose a hybrid multiqubit configuration consisting of nine transmon qubits organized into interior and exterior groups, interconnected via a flux tunable qubit and a network of distributed resonators. The interior qubits along with tunable qubit form an entanglement core, while the exterior qubits operate in the dispersive regime under large detuning to enable readout. The degree of entanglement can be dynamically tuned by adjusting the coupling between the central tunable qubit and the interior qubits. The total Hamiltonian includes all significant coupling contributions, encompassing effective exchange interactions among interior and exterior qubits, as well as their mediated couplings through interface resonators. By numerically solving the complete Hamiltonian alongside the Lindblad master equation, the system dynamics are characterized, allowing evaluation of both spectroscopic features and separation fidelity. Simulation results demonstrate that the proposed design maintains strong entanglement by creating the avoided-crossing region while sustaining measurement fidelity around 0.995 under realistic noise conditions. These findings confirm that entanglement strength and readout fidelity can be co-optimized within a single, reconfigurable architecture, establishing a viable route toward high-performance and scalable superconducting quantum processors.
This study introduces a superconducting quantum chip architecture designed to simultaneously preserve entanglement and readout fidelity, addressing one of the key trade-offs in the development of scalable quantum hardware. In conventional quantum circuits, strong qubit qubit coupling enhances entanglement but often leads to undesired crosstalk, dephasing, and reduced measurement fidelity. To mitigate these effects, we propose a hybrid multiqubit configuration consisting of nine transmon qubits organized into interior and exterior groups, interconnected via a flux tunable qubit and a network of distributed resonators. The interior qubits along with tunable qubit form an entanglement core, while the exterior qubits operate in the dispersive regime under large detuning to enable readout. The degree of entanglement can be dynamically tuned by adjusting the coupling between the central tunable qubit and the interior qubits. The total Hamiltonian includes all significant coupling contributions, encompassing effective exchange interactions among interior and exterior qubits, as well as their mediated couplings through interface resonators. By numerically solving the complete Hamiltonian alongside the Lindblad master equation, the system dynamics are characterized, allowing evaluation of both spectroscopic features and separation fidelity. Simulation results demonstrate that the proposed design maintains strong entanglement by creating the avoided-crossing region while sustaining measurement fidelity around 0.995 under realistic noise conditions. These findings confirm that entanglement strength and readout fidelity can be co-optimized within a single, reconfigurable architecture, establishing a viable route toward high-performance and scalable superconducting quantum processors.
Abstract A hybrid physics–machine-learning framework is introduced for the joint optimization of separate fidelity and Grover algorithm performance in superconducting quantum processors. The method combines a Hamiltonian-based open-quantum-system model of a two-qubit architecture coupled through a bus resonator with a QGHNN. Readout performance is evaluated via the Lindblad master-equation simulation of the dispersive measurement process, in which state-dependent resonator dynamics are mapped to realistic I/Q distributions and classified to estimate single-shot measurement fidelity. In parallel, algorithmic performance is assessed by simulating a two-qubit Grover search circuit in the presence of dissipation and dephasing, using effective cross-Kerr interactions derived from the underlying circuit parameters. A physically constrained dataset is constructed by sampling of some critical variables relevant to system. The QGHNN is trained to learn the nonlinear relationship between device parameters and the dual objectives of readout (separation) fidelity and Grover success probability. Gradient-based optimization is then carried out directly in parameter space using the trained network, yielding operating points that simultaneously improve measurement distinguishability and Grover algorithm accuracy. Simulation results demonstrate that the readout separation fidelity exceeds 99.4%, while the Grover success probability reaches approximately 86%, and this is comparable with the accuracy achieved by IBM Q5 Tenerife processor. Finally, the optimized parameters are used to implement the quantum circuit layout in Qiskit Metal, and their validity is further confirmed through EPR-based certification.
To reduce circuit depth when executing Quantum algorithms, it is necessary to maximize qubit connectivity on a near-term quantum processor. While addressing this, we also need to ensure high gate fidelity, suppression of unwanted ZZ cross-talk, a compact layout footprint, and minimal control hardware complexity to support scalability. In current superconducting quantum chips, fixed coupling is used as it is easier to scale, but it is limited by unwanted static ZZ interaction during single qubit operations, which degrades system performance. To overcome these challenges, we have introduced a first-of-its-kind hybrid tunable-coupling architecture that connects four fixed-frequency transmon qubits using a single coupler. This hybrid coupler uses off-resonant Stark drives to tune ZZ strength between qubit pairs. Experimentally backed simulation results indicate that our proposed hybrid design maximizes the qubit connectivity while reducing control overhead. This design achieves a near 20% reduction in circuit depth compared to IBM's Heavy-Hexagonal layout, showing its potential for scalability.
Fluxonium qubits combine long coherence times with strong anharmonicity, making them a promising platform for scalable superconducting quantum processors. Recent experiments have demonstrated high-fidelity operations in multi-qubit processors while suppressing stray qubit interactions using fluxonium-transmon-fluxonium (FTF) architectures. However, scaling such systems to larger arrays is constrained by a trade-off between achievable coupling strength, crosstalk suppression and qubit-qubit spacing required for wiring in a two-dimensional architecture. Multimode couplers, such as the double-transmon coupler (DTC), provide a promising pathway to overcome this limitation by enabling stronger interactions without compromising qubit spacing and isolation. Here, we develop a quantitative design framework for fluxonium-based quantum processors employing DTCs. Central to this work is a frequency-partitioned architecture that places qubit transitions, tunable-coupler excitations, and resonator modes in well-separated spectral regions. This structured allocation reduces parameter interdependence and enables the concurrent optimization of gate operations, readout, and qubit reset. By formulating device design as a multi-objective optimization problem under realistic experimental constraints and fabrication-induced disorder, we develop a tractable sequential workflow and determine a feasible parameter regime that simultaneously supports high-fidelity single- and two-qubit gates, fast qubit reset, and robust dispersive readout. These results establish a system-level architectural methodology that links circuit parameters to processor-level performance, and provide an experimentally actionable pathway toward scalable fluxonium quantum processors.
The technological development of hardware heading toward universal fault-tolerant quantum computation requires a large-scale processing unit with high performance. While fluxonium qubits are promising with high coherence and large anharmonicity, their scalability has not been systematically explored. In this work, we propose a superconducting quantum information processor based on compact high-coherence fluxoniums with suppressed crosstalk, reduced design complexity, improved operational efficiency, high-fidelity gates, and resistance to parameter fluctuations. In this architecture, the qubits are readout dispersively using individual resonators connected to a common bus and manipulated via combined on-chip RF and DC control lines, both of which can be designed to have low crosstalk. A multi-path coupling approach enables exchange interactions between the high-coherence computational states and at the same time suppresses the spurious static ZZ rate, leading to fast and high-fidelity entangling gates. We numerically investigate the cross resonance controlled-NOT and the differential AC-Stark controlled-Z operations, revealing low gate error for qubit-qubit detuning bandwidth of up to 1 GHz. Our study on frequency crowding indicates high fabrication yield for quantum processors consisting of over thousands of qubits. In addition, we estimate low resource overhead to suppress logical error rate using the XZZX surface code. These results promise a scalable quantum architecture with high performance for the pursuit of universal quantum computation.
Dispersive readout, the current standard for measuring superconducting qubits, relies on relatively easy to engineer, static transverse coupling between a qubit and a detuned cavity mode. However, this method requires circuit design trade-offs between qubit-cavity coupling, cavity-feedline coupling, detuning, and the resultant decoherence introduced by the cavity mode. Additionally, the criteria for performing quantum nondemolition measurements, including reduced cavity photon numbers, further limits speed and fidelity. In this work, we introduce a circuit with pulse-tunable qubit-cavity and cavity-feedline couplings so that the entire qubit-measurement process can be fully optimized. Here, the core measurement process resembles a quantum gate operation between the qubit and the cavity, with the cavity acting like an ancilla, storing the qubit-state information. To fully explore time-dependent effects of the full qubit-cavity dynamics, we go beyond the rotating-wave, Jaynes-Cummings, or dispersive approximations, to develop a pulsed-measurement protocol. In addition, we propose a realistic circuit architecture that can provide a very fast, high-fidelity, QND measurement with near-unit efficiency.
Achieving high-fidelity qubit readout and reset while maintaining qubit coherence is crucial for quantum error correction and advanced quantum algorithms. Here, we design and experimentally demonstrate a scalable architecture based on frequency-tunable nonlinear Purcell filters, which enables flexible readout and rapid unconditional reset of multiple superconducting qubits. Our readout protocol dynamically adjusts the effective linewidth of the readout resonator through a tunable Purcell filter, optimizing the signal-to-noise ratio during measurement while suppressing photon noise during idle periods. Combined with a multilevel readout protocol, we achieve the highest readout fidelity of 99.3% without any quantum-limited amplifier, even with a small dispersive shift. Moreover, by leveraging a reset channel formed via the adjacent coupling between the filter and the coupler, we realize unconditional qubit reset of both leakage-induced |2⟩ and |1⟩ states within 200 ns and reset of the |1⟩ state alone within 75 ns, with error rates ≤1%. The filter also mitigates both photon-induced dephasing and the Purcell effect, thereby preserving qubit coherence. This scalable Purcell filter architecture shows exceptional performance in qubit readout, reset, and protection, marking it as a promising hardware component for advancing fault-tolerant quantum computing systems.