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International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

A Fractional-N PLL Frequency Synthesizer for Qubit Readout and Control Architectures

Roque Fernández Maldonado, Uxua Esteban Eraso, F. Aznar, C. Aldea, Santiago Celma, Carlos Sánchez‐Azqueta

Published Jun 1, 2026• 0 citations
Publisher
DOI
10.1109/smacd70206.2026.11647821

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This paper presents a comprehensive cryogenic analog signal processing architecture designed for superconducting qubit control and quantum state readout operating at 4 Kelvin. The proposed system implements a complete bidirectional signal path bridging room-temperature digital controllers with quantum processors at millikelvin stages. The control path incorporates a Phase-Locked Loop (PLL) for stable local oscillator generation, In-phase/Quadrature (I/Q) modulation for precise qubit gate operations, and a cryogenic power amplifier for signal conditioning. The readout path features a Low Noise Amplifier (LNA) with 14 dB gain and 8-Phase Shift Keying (8-PSK) demodulation for quantum state discrimination. All circuit blocks are designed and validated through SPICE simulations employing cryogenic MOSFET models at 180nm that account for carrier freeze-out, threshold voltage elevation, and enhanced mobility at 4 K. Simulation results demonstrate successful end-to-end signal integrity with I/Q phase error below 2°, image rejection ratio exceeding 35~dB, and symbol error rate below 10−610^{-6}10−6. This work provides a modular, simulation-validated framework for scalable cryogenic quantum control systems.