Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

A Physics-Grounded EDA-ML Framework for Designing and Validating Quantum Language Model Circuits on Superconducting Hardware

Manoj Gupta

Published Jan 1, 2026• 0 citations
Publisher
DOI
10.2139/ssrn.7014318

Related papers

Fabless Quantum Chip Design and Commercial Production

Cai, Ling Qiao, Bin Yang +6 more

This paper proposes a fabless quantum-chip design and production architecture for superconducting quantum computing, centered on the SPICE-Q multiphysics simulation framework. The proposed ecosystem connects process-certified quantum PDKs, parameterized device cells, traceable model cards, SPICE-Q physical modeling languages, unified Q-EDA flows, foundry sign-off rules, cryogenic test feedback, and reusable quantum IP. In this model, design firms do not merely outsource fabrication; they prepare verified tape-outs under standardized process constraints and calibrated physical models. Its economic value lies in reducing repetitive device debugging, process exploration, and low-level layout effort, while its feasibility depends on PDK maturity, foundry yield, cryogenic test throughput, model-prediction accuracy, data-feedback mechanisms, and IP licensing boundaries. We argue that superconducting quantum chips can move from the current largely vertically integrated development model toward a fabless-foundry ecosystem only when hardware design is supported by standardized, verifiable, and reusable software and process interfaces. The required pillars are certified PDKs, PCell-based parameterized design, SPICE-Q cross-physics simulation, end-to-end Q-EDA automation, and a tradable quantum-IP market. By adapting lessons from the classical semiconductor industry to quantum hardware, this framework defines a path toward scalable, manufacturable, and commercially reusable superconducting quantum-chip design.

quant-pharXiv:2606.17956•Jun 17, 2026•0 citations

Engineered quantum systems for quantum computation with superconducting circuits

Dat Thanh Le

•Aug 31, 2022•0 citations

Superconducting Quantum Circuits for Quantum Computing and Quantum Simulation

Jens Koch

Bulletin of the American Physical Society•Mar 6, 2020•0 citations

Modeling of superconductive circuits for quantum computers

Konstantinos Nikellis, Stefanos Stefanou, Y. Moisiadis

Superconductive silicon is one of the most promising technologies for implementing practical quantum computers. EDA vendors can assist in the quantum hardware designers’ endeavors by providing solutions that can lead to designs of increased qubit quality. This technical report presents a new modeling engine that is able to model tens to hundreds of physical qubits capturing all coupling and crosstalk between them, thus providing the quantum hardware designers with vital information on the quality of their designs.

Emerging Tech Conference Edge Intelligence•Apr 4, 2025•0 citations

A Representative Framework for Implementing Quantum Finite Automata on Real Devices

Aliya Khadieva, Özlem Salehi, Abuzer Yakaryılmaz

arXiv:2406.11360•Lecture notes in computer science•Jan 1, 2024•9 citations

AI/ML-Driven Electronic Design Automation Framework for Quantum-Aware VLSI Circuit Synthesis and Optimization in High-Performance Computing Applications

Increased development of high-performance computing (HPC) has increased the pressure on new paradigms in VLSI circuit design, as device scaling is approaching scaling limits where quantum effects become important.Conventional electronic design automation (EDA) processes have difficulties in dealing with nonlinear interactions that occur when quantum tunnelling, leakage currents, and probabilistic switching are also present in the deeply scaled technology.To overcome them, this paper suggests an all-encompassing AI/ML-based EDA architecture, which incorporates quantum-aware modelling, predictive synthesis, and adaptive optimization of future HPC-oriented next-generation VLSI systems.The framework has incorporated machine learning (ML)-based parametric estimation, reinforcement learning (RL) on layout exploration, and physics-guided neural models: nonclassical effects in nanoscale transistors.Furthermore, the system uses generative learning algorithms to create multiobjective design trade-offs in terms of timing, power, area, and quantum reliability.The hybrid digital-quantum design flow is presented, allowing to easily interchange the classical EDA operations and quantum-inspired device tests.Nanometer-scale benchmark circuit confirmation of the efficiency of synthesis, accuracy of leakage prediction, and rate of convergence of optimization are shown to be much enhanced with respect to more traditional EDA pipelines.The given methodology puts the emphasis on the role of intelligent automation as the means of guiding the VLSI research toward the point of quantum-awareness as the key to ensuring reliability, scalability, and energy efficiency in an HPC system.

Journal of VLSI Circuits and Systems•May 1, 2025•0 citations
This paper proposes a fabless quantum-chip design and production architecture for superconducting quantum computing, centered on the SPICE-Q multiphysics simulation framework. The proposed ecosystem connects process-certified quantum PDKs, parameterized device cells, traceable model cards, SPICE-Q physical modeling languages, unified Q-EDA flows, foundry sign-off rules, cryogenic test feedback, and reusable quantum IP. In this model, design firms do not merely outsource fabrication; they prepare verified tape-outs under standardized process constraints and calibrated physical models. Its economic value lies in reducing repetitive device debugging, process exploration, and low-level layout effort, while its feasibility depends on PDK maturity, foundry yield, cryogenic test throughput, model-prediction accuracy, data-feedback mechanisms, and IP licensing boundaries. We argue that superconducting quantum chips can move from the current largely vertically integrated development model toward a fabless-foundry ecosystem only when hardware design is supported by standardized, verifiable, and reusable software and process interfaces. The required pillars are certified PDKs, PCell-based parameterized design, SPICE-Q cross-physics simulation, end-to-end Q-EDA automation, and a tradable quantum-IP market. By adapting lessons from the classical semiconductor industry to quantum hardware, this framework defines a path toward scalable, manufacturable, and commercially reusable superconducting quantum-chip design.
Superconductive silicon is one of the most promising technologies for implementing practical quantum computers. EDA vendors can assist in the quantum hardware designers’ endeavors by providing solutions that can lead to designs of increased qubit quality. This technical report presents a new modeling engine that is able to model tens to hundreds of physical qubits capturing all coupling and crosstalk between them, thus providing the quantum hardware designers with vital information on the quality of their designs.
Increased development of high-performance computing (HPC) has increased the pressure on new paradigms in VLSI circuit design, as device scaling is approaching scaling limits where quantum effects become important.Conventional electronic design automation (EDA) processes have difficulties in dealing with nonlinear interactions that occur when quantum tunnelling, leakage currents, and probabilistic switching are also present in the deeply scaled technology.To overcome them, this paper suggests an all-encompassing AI/ML-based EDA architecture, which incorporates quantum-aware modelling, predictive synthesis, and adaptive optimization of future HPC-oriented next-generation VLSI systems.The framework has incorporated machine learning (ML)-based parametric estimation, reinforcement learning (RL) on layout exploration, and physics-guided neural models: nonclassical effects in nanoscale transistors.Furthermore, the system uses generative learning algorithms to create multiobjective design trade-offs in terms of timing, power, area, and quantum reliability.The hybrid digital-quantum design flow is presented, allowing to easily interchange the classical EDA operations and quantum-inspired device tests.Nanometer-scale benchmark circuit confirmation of the efficiency of synthesis, accuracy of leakage prediction, and rate of convergence of optimization are shown to be much enhanced with respect to more traditional EDA pipelines.The given methodology puts the emphasis on the role of intelligent automation as the means of guiding the VLSI research toward the point of quantum-awareness as the key to ensuring reliability, scalability, and energy efficiency in an HPC system.