Arithmetic units constitute fundamental components of reversible-computing architectures, where circuit complexity, resource utilization, and hardware realizability are critical design considerations. This work presents a parity-preserving reversible 2 × 2 Vedic multiplier architecture constructed using existing N1, RF, A, and N3 reversible logic blocks and hierarchically extended to realize a 4 × 4 multiplier through a parity-preserving 4-bit ripple-carry adder structure. Comparative evaluation demonstrates competitive performance relative to representative reversible multiplier architectures. To evaluate implementation-oriented characteristics, the proposed architecture was mapped to the Clifford+T gate set and analyzed using hardware-aware resource metrics. The resulting realization exhibits a T-count of 35, a T-depth of 19, and a transpiled circuit depth of 55 without requiring SWAP operations. The proposed 2 × 2 multiplier core was experimentally validated on the IBM Quantum ibm_kingston superconducting processor based on the Heron r2 architecture through complete truth-table verification across all sixteen input combinations using 1024 measurement shots per experiment. The dominant measured output matched the expected multiplication result in every case, yielding an average success probability of 70.12% and an average Bhattacharyya fidelity of 0.7012. Calibration-based fidelity estimation using backend-reported gate fidelities yielded an estimated circuit fidelity of 0.7485, which is consistent with the experimentally observed average success probability of 70.12%. Hardware-aware circuit characterization, noise-model evaluation, and fidelity analysis were performed to assess implementation behavior under practical execution conditions. In addition, application-level arithmetic demonstrations involving Low-bit-width image-processing arithmetic examples were used solely as application-level demonstrations of multiplier functionality and do not constitute a complete quantum image-processing framework. The obtained results confirm the functional correctness, hardware compatibility, and resource efficiency of the proposed architecture and provide practical insights for future reversible arithmetic and quantum-computing applications.
Arithmetic units constitute fundamental components of reversible-computing architectures, where circuit complexity, resource utilization, and hardware realizability are critical design considerations. This work presents a parity-preserving reversible 2 × 2 Vedic multiplier architecture constructed using existing N1, RF, A, and N3 reversible logic blocks and hierarchically extended to realize a 4 × 4 multiplier through a parity-preserving 4-bit ripple-carry adder structure. Comparative evaluation demonstrates competitive performance relative to representative reversible multiplier architectures. To evaluate implementation-oriented characteristics, the proposed architecture was mapped to the Clifford+T gate set and analyzed using hardware-aware resource metrics. The resulting realization exhibits a T-count of 35, a T-depth of 19, and a transpiled circuit depth of 55 without requiring SWAP operations. The proposed 2 × 2 multiplier core was experimentally validated on the IBM Quantum ibm_kingston superconducting processor based on the Heron r2 architecture through complete truth-table verification across all sixteen input combinations using 1024 measurement shots per experiment. The dominant measured output matched the expected multiplication result in every case, yielding an average success probability of 70.12% and an average Bhattacharyya fidelity of 0.7012. Calibration-based fidelity estimation using backend-reported gate fidelities yielded an estimated circuit fidelity of 0.7485, which is consistent with the experimentally observed average success probability of 70.12%. Hardware-aware circuit characterization, noise-model evaluation, and fidelity analysis were performed to assess implementation behavior under practical execution conditions. In addition, application-level arithmetic demonstrations involving Low-bit-width image-processing arithmetic examples were used solely as application-level demonstrations of multiplier functionality and do not constitute a complete quantum image-processing framework. The obtained results confirm the functional correctness, hardware compatibility, and resource efficiency of the proposed architecture and provide practical insights for future reversible arithmetic and quantum-computing applications.
Abstract Quantum computing has attracted increased attention in recent years owing to substantial advancements in quantum algorithms and system architecture. Quantum algorithms are implemented using quantum circuits. These circuits include an intrinsic reversibility and often have a substantial Boolean component that requires synthesis. A crucial characteristic of reversible circuits is the preservation of parity. Parity-preserving logic is a category that maintains the parity of both inputs and outputs, facilitating the detection of permanent and transient errors. Multiplier circuits are essential components in digital computing systems, playing a crucial role in the development of various hardware, including arithmetic circuits. This paper first introduces a novel block based on a transformationbased synthesis technique from the elementary quantum gates. Then it proposes a distinctive 2×2 parity-preserving reversible quantum Vedic multiplier based on the recommended block and prior gates. In addition, further designs of Vedic multipliers are provided, encompassing 4-bit, 8-bit, and 16-bit configurations. We illustrate that our design brings superior outcomes regarding quantum cost (QC), constant inputs (CI) count, CNOT-V/V + count, garbage outputs (GO) count, and gate count (GC) in comparison to earlier designs. This study achieves an average decrease of 23.09%, 37.51%, 37.51%, 54.89%, and 19.38% in QC, CI, GO, GC, and CNOT-V/V + count, respectively. Furthermore, all suggested circuits undergo appraisal and validation within the IBM quantum laboratory.
Quantum computers provide considerable potential to enhance computing technology, anticipated to surpass conventional computers by resolving intricate challenges that existing systems cannot tackle. They use quantum algorithms for improved performance and depend on reversible computations based on quantum physics and linear algebra. In contrast to traditional computing, which may include irreversible processes, quantum computing relies on unitary operations that are fundamentally reversible. The parity-preserving feature enables the identification of both permanent and transient defects within circuits. The parity-preserving feature ensures that the input and output states are equal in reversible circuits. Vedic multipliers offer a crucial foundation in the design and implementation of digital circuits, recognized for their speed, efficiency, ease of calculations, reduction of errors, and broad applicability. Prior investigations of quantum Vedic multipliers have faced obstacles like elevated Quantum Cost (QC), substantial Garbage Output (GO), Constant Input (CI), augmented Gate Count (GC), and CNOT-V/V+ count, resulting in more resource use and implementation intricacy. These inefficiencies hinder the scalability and feasibility of quantum multipliers in high-performance computing applications. A proposed solution to these issues is to introduce a cost-effective, parity-preserving reversible quantum block synthesized through an established method that produces a network list of multi-controlled Toffoli (MCT) gates. This Toffoli-based network is then optimized using various techniques, ultimately transforming it into a network of fundamental quantum gates. This approach decreases quantum expenses, eliminates unnecessary outputs, and enhances quantum gate efficiency. Integrating this innovative technique into the reversible quantum Vedic multipliers offers a more efficient, cost-effective, and scalable solution than current approaches. All proposed designs, such as a half adder-subtractor, a ripple carry adder (RCA), and two-bit and four-bit Vedic multipliers, are suggested based on functional blocks and pre-existing components. The suggested structures undergo evaluation in comparison to existing state-of-the-art procedures, demonstrating their cost-effectiveness. The observed average savings for two-bit and four-bit Vedic multipliers, with respect to QC, number of CNOT-V/V+ count, GO, CI, and GC, are 20.01%, 19.38%, 37.51%, 37.51%, and 54.89%, and 22.71%, 18.78%, 27.23%, 31.10%, and 42.38%, respectively when compared to previous studies. Furthermore, all suggested circuits are evaluated and confirmed using the IBM quantum laboratory.
Abstract Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.
Abstract This paper presents a reversible, n‑bit Quantum Arithmetic Logic Unit (QALU) implemented in Qiskit that supports a classical ALU‑like instruction set: ADD, SUB, CMP, AND/OR/XOR and their negations, unary NOT, shifts and rotates, and operand passthrough. The QALU outputs a result register and status flags N, Z, C, V (negative, zero, carry/no‑borrow, signed overflow) and emits explicit comparison outputs EQ, LT u , LT s . The design is modular and operation‑selectable at compile time, enabling clean verification and resource accounting. To evaluate fault‑tolerant efficiency, the circuits are decomposed into a Clifford + T basis and measure T‑count alongside CX‑count and depth. Exhaustive verification on Aer (matrix‑product‑state simulation) confirms correctness for all input pairs for n = 4 across 16 operations. Hardware experiments on IBM Quantum (limited to n = 2) demonstrate end‑to‑end execution with dynamical decoupling and gate twirling, and readout mitigation via mthree. An analytical scaling discussion grounded in ripple‑carry adder theory and known Toffoli/T‑gate constructions is further provided. These results show that a practical, verifiable QALU with flags and compare can be implemented within Qiskit while exposing meaningful fault‑tolerant metrics and hardware‑realistic performance characterization. Key findings from the provided implementation artifacts: (1) Aer exhaustive verification (n = 4): the QALU was exhaustively tested over all 2 2n =256 input pairs for each of 16 operations (4096 total tests), with 0 mismatches against a classical reference model. (2) Resource metrics (n = 4): after transpilation to a Clifford + T‑style basis {cx, h, s, sdg, x, z, t, tdg} at optimization level 3, the highest‑cost operations (ADD, SUB, CMP) report T‑count = 86, CX‑count ≈ 102–106, and depth ≈ 138 on a 24‑qubit circuit instance (including flags and MCX ancillae). (3) IBM hardware test (n = 2): on an automatically selected IBM backend (ibm_torino) using dynamical decoupling and gate twirling plus mthree readout mitigation, an exhaustive run over all 256 circuits yielded raw correctness 91.41% and mitigated correctness 91.02% (slightly worse post‑mitigation, consistent with practical tradeoffs where mitigation noise/calibration drift can dominate at small sizes).
Reversible logic, by enabling computations without loss of information, offers a promising approach to significantly reducing energy dissipation, making it a key technology for low-power and quantum computing systems. Parity-preserving reversible circuits further enhance reliability, enabling fault detection in nanoscale systems. Multiplication, a fundamental operation in computing and signal processing, benefits significantly from efficient reversible designs. However, existing reversible Vedic multipliers often suffer from excessive Quantum Cost (QC), Garbage Outputs (GO), and Constant Inputs (CI). This paper proposes two new 2-bit parity-preserving reversible quantum Vedic multipliers, serving as the foundational block for scalable n-bit multipliers, that are enhanced to reduce quantum metrics without compromising performance. The proposed circuits are simulated using the Quirk tool to test their correct functionality. Comparative analysis shows that the best proposed design outperforms existing architectures on average by 34%, 53%, and 9% in constant inputs, garbage outputs, and quantum cost, respectively, providing a fault-tolerant, cost-efficient, and scalable solution for next-generation quantum computing systems.
Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.