We introduce the Hot Processing Unit (HPU), a unified programming model for dissipative quantum hardware. Five physically distinct substrate classes -- PT-symmetric photonic chips (HPU-P), bosonic cat qubits (HPU-B), radical-pair molecular processors (HPU-R), non-Hermitian electrical circuits (HPU-C), and exceptional-point (EP) sensor arrays (HPU-E) -- share a common computational structure: they execute programmes in which gain, loss, and complex inverse temperature beta are first-class operations. We show that the Raven Instruction Set Architecture (ISA) is the natural HPU instruction set, with SNAP-count (the number of tier-promotion events) as the resource metric analogous to T-count in fault-tolerant quantum computing. The GPU unified diverse parallel hardware under CUDA; the HPU unifies diverse dissipative hardware under the Raven ISA. We present the HPU architecture, a five-substrate compiler pipeline, and five benchmark algorithms -- culminating in the observation that EP sensing (SNAP-count = 0) is the first demonstrated HPU algorithm, and that autonomous quantum error correction on cat qubits is the route to Shor's algorithm on HPU hardware.
We introduce the Hot Processing Unit (HPU), a unified programming model for dissipative quantum hardware. Five physically distinct substrate classes -- PT-symmetric photonic chips (HPU-P), bosonic cat qubits (HPU-B), radical-pair molecular processors (HPU-R), non-Hermitian electrical circuits (HPU-C), and exceptional-point (EP) sensor arrays (HPU-E) -- share a common computational structure: they execute programmes in which gain, loss, and complex inverse temperature beta are first-class operations. We show that the Raven Instruction Set Architecture (ISA) is the natural HPU instruction set, with SNAP-count (the number of tier-promotion events) as the resource metric analogous to T-count in fault-tolerant quantum computing. The GPU unified diverse parallel hardware under CUDA; the HPU unifies diverse dissipative hardware under the Raven ISA. We present the HPU architecture, a five-substrate compiler pipeline, and five benchmark algorithms -- culminating in the observation that EP sensing (SNAP-count = 0) is the first demonstrated HPU algorithm, and that autonomous quantum error correction on cat qubits is the route to Shor's algorithm on HPU hardware.
Quantum computing has been, from its inception, a programme of refrigeration: isolate the system, suppress dissipation, drive the physical temperature toward zero. This programme has achieved remarkable results, and the researchers who built it deserve full credit. But it is incomplete. Real quantum systems are open. Biology runs its most precise quantum computations -- kinetic proofreading, photosynthetic energy transfer, avian magnetoreception -- in warm, wet, dissipative environments, not in dilution refrigerators. Exceptional-point sensors already outperform classical sensors by exploiting, rather than suppressing, gain and loss. We coin the term hot quantum computing for computation that treats dissipation as a resource rather than a defect, and we describe the instruction set architecture -- the Raven ISA, built on the Motive ISA -- that gives it a rigorous programming model. Hot quantum is not noisy quantum: the distinction is between a leaky pipe (still trying to be airtight) and a water wheel (working because of the flow). The field has been jumping out of the bath. It is time to embrace it.
Every major quantum programming language restricts to unitary operations and Hermitian Hamiltonians. This is understandable: unitarity is tractable, elegant, and sufficient for standard gate-model quantum computing. But real quantum systems are open, dissipative, and non-Hermitian. By refusing to engage with loss, the field is in a bind -- unable to express PT-symmetric computation, Lindblad dynamics, exceptional-point algorithms, or even the classical limit of quantum mechanics. We identify the missing primitive: BIND (the Frobenius comultiplication delta: A -> A tensor A), and the missing parameter: beta (the semiring grade interpolating between tropical, quantum, and PT-symmetric regimes). The Raven ISA is the minimal non-unitary extension of the Heunen et al. phase language that adds these two ingredients. It implements five computational advantages unavailable to unitary languages, and subsumes all existing quantum programming languages as the beta = i special case. It is time to find BIND.
To harness the power of quantum computing (QC) in the near future, tight and efficient integration of QC with high performance computing (HPC) infrastructure (both on the software (SW) and the hardware (HW) level) is crucial. This paper addresses the development of a unified quantum platform (UQP) and how it is being integrated into the HPC ecosystem. It builds on the concepts of hybrid high performance computing - quantum computing (HPCQC) workflows and a unified HPCQC toolchain, introduced in our previous work and makes the next needed step: it unifies the low-level interface between the existing classical HPC systems and the emerging quantum hardware technologies, including but not limited to machines based on superconducting qubits, neutral atoms or trapped ions. The UQP consists of three core components: a runtime library, an instruction set architecture (ISA) and a quantum control processor (QCP) micro-architecture. In particular, this work contributes a unified HPCQC runtime library that bridges the gap between programming systems built on quantum intermediate representation (QIR) standard with a novel, unified hybrid ISA. It then introduces the initial extension of an ISA and QCP micro-architecture to be platform and technology agnostic and enables it as an efficient execution platform. The UQP has been verified to ensure correctness. Further, our performance analysis shows that the execution time and memory requirements of the runtime library scale super-linearly with number of qubits, which is critical to support scalability efforts in OC hardware.
Fault tolerance is an indispensable prerequisite for constructing large-scale universal quantum computers. Drawing philosophies from classical computer architecture, this paper presents a hardware-agnostic three-layer high-level architectural framework for generic fault-tolerant quantum computation. Guided by the real execution workflows of fault-tolerant quantum algorithms, the proposed model is decoupled from specific physical qubit hardware platforms and quantum error correction codes, serving as a universal abstract standard rather than a platform-specific implementation scheme. Special attention is devoted to the intermediate Fault-Tolerance Layer, which serves as the architectural bridge between application-level logical programs and hardware-level execution. We systematically characterize its five internal components, the interfaces and data exchanged among them, and the execution, correction, and adaptation paths that together enable logical synthesis, fault-tolerant resources management, decoding, and runtime fault-tolerant control. An end-to-end example is further provided to illustrate the full-stack operating pipeline of fault-tolerant quantum algorithms under this framework. Given the increasing emphasis on modular, heterogeneous, and cross-layer fault-tolerant quantum systems, our architecture provides a unified foundational model for organizing such designs.
The Raven ISA tier (β∈ℂ, PT-symmetric) is shown to be accessible on any existing quantum computer via a hybrid classical-quantum protocol: standard unitary circuits supply the imaginary-β quantum phases, while classical post-measurement reweighting by Boltzmann factors e^(−σE_k) supplies the real-β dissipation. The composite estimator reconstructs the complex-β partition function Z(σ+it) with no additional qubits, no postselection overhead, and gate cost identical to a standard Meld circuit. Three application classes are demonstrated: RavenRank (dissipation-weighted ranking), PT-symmetric eigensolvers for non-Hermitian matrices, and exceptional-point search with sub-Grover query complexity.
In this paper we propose a model of a programmable quantum processing device realizable with existing nano-photonic technologies. It can be viewed as a basis for new high performance hardware architectures. Protocols for physical implementation of device on the controlled photon transfer and atomic transitions are presented. These protocols are designed for executing basic single-qubit and multi-qubit gates forming a universal set. We analyze the possible operation of this quantum computer scheme. Then we formalize the physical architecture by a mathematical model of a Quantum Processing Unit (QPU), which we use as a basis for the Quantum Programming Framework. This framework makes it possible to perform universal quantum computations in a multitasking environment.