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Correlation Between Layer II Structural Metrics and Qiskit Transpilation Costs in IBM Heavy-Hex Architectures

Pedro Pelegrini

Published Jun 15, 2026• 0 citations
Publisher

Abstract

Technical report investigating correlations between AlgebraQ Layer II structural observables and Qiskit transpilation costs on IBM Heavy-Hex architectures. The study analyzes QFT, GHZ and hardware-efficient circuits across Heavy-Hex coupling maps generated through Qiskit's official implementation.
DOI
10.5281/zenodo.20708012

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Compiling a given quantum algorithm into a target hardware architecture is a challenging optimization problem. The compiler must take into consideration the coupling graph of physical qubits and the gate operation dependencies. The existing noise in hardware architectures requires the compilation to use as few running cycles as possible. Existing approaches include using SAT solver or heuristics to complete the mapping but these may cause the issue of either long compilation time (e.g., timeout after hours) or suboptimal compilation results in terms of running cycles (e.g., exponentially increasing number of total cycles). In this paper, we propose an efficient mapping approach for Quantum Fourier Transformation (QFT) circuits over the existing IBM heavy-hex architecture. Such proposal first of all turns the architecture into a structure consisting of a straight line with dangling qubits, and then do the mapping over this generated structure recursively. The calculation shows that there is a linear depth upper bound for the time complexity of these structures and for a special case where there is 1 dangling qubit in every 5 qubits, the time complexity is 5N+O(1). All these results are better than state of the art methods.

arXiv:2402.09705•Feb 15, 2024•1 citation
This technical note investigates whether Layer II structural diagnostics can predict transpilation costs in IBM Heavy-Hex quantum architectures before compilation is performed. The study evaluates Heavy-Hex coupling maps generated through Qiskit for distances d = 3, 5, 7, and 9. Structural observables are computed directly from the architecture graph and compared against normalized transpilation metrics obtained from Quantum Fourier Transform (QFT), GHZ-state preparation, and Hardware-Efficient Ansatz (HEA) circuits. A leave-one-out validation procedure is used to assess predictive capability on unseen architecture instances. Results indicate that mediation, normalized structural cost, and feasibility observables contain measurable predictive information regarding transpilation overhead. The strongest performance is observed for HEA and GHZ workloads, where several prediction targets achieve low error levels. The benchmark provides preliminary evidence that circuit-independent structural observables may support predictive assessment of compilation costs during early-stage quantum architecture evaluation.
We present a novel architecture-aware transpilation method for exact general unitary gate synthesis on superconducting quantum hardware. Our approach is tightly integrated with the optimized block-ZXZ decomposition, exploiting its recursive structure to make hardware-aware decisions at each level of the recursion rather than treating transpilation as an independent post-processing step. The method introduces three key techniques: a greedy qubit mapping strategy that minimizes pairwise distances between physical qubits, an adaptive Gray code selection combined with qubit swapping that optimizes the construction of uniformly controlled Rz gates for the target topology, and a heuristic for reducing CNOT gates by exploiting the structure of long-range CNOT ladders. We benchmark our method against TKet, Qiskit, and Pennylane on the 20-qubit IQM Garnet (square lattice) and the 156-qubit IBM Marrakesh (heavy-hex) architectures with qubit counts ranging from 3 to 11. Our method achieves CNOT count reductions of up to 36 percent on the IQM Garnet and up to 34 percent on the IBM Marrakesh compared to the best competing transpiler, while simultaneously achieving transpilation speedups of up to 553x. Furthermore, our method is the only one capable of transpiling circuits beyond 10 qubits within a 30-minute time limit across both architectures.
Compiling a given quantum algorithm into a target hardware architecture is a challenging optimization problem. The compiler must take into consideration the coupling graph of physical qubits and the gate operation dependencies. The existing noise in hardware architectures requires the compilation to use as few running cycles as possible. Existing approaches include using SAT solver or heuristics to complete the mapping but these may cause the issue of either long compilation time (e.g., timeout after hours) or suboptimal compilation results in terms of running cycles (e.g., exponentially increasing number of total cycles). In this paper, we propose an efficient mapping approach for Quantum Fourier Transformation (QFT) circuits over the existing IBM heavy-hex architecture. Such proposal first of all turns the architecture into a structure consisting of a straight line with dangling qubits, and then do the mapping over this generated structure recursively. The calculation shows that there is a linear depth upper bound for the time complexity of these structures and for a special case where there is 1 dangling qubit in every 5 qubits, the time complexity is 5N+O(1). All these results are better than state of the art methods.