Abstract We provide a circuit-level numerical validation of the three-sheet time-multiplexed FCC sheet code, a quantum low-density parity-check (qLDPC) construction with parameters [[3L 3 , 6L, L]] derived from the three triad sheets of the face-centered cubic lattice. At L = 4 the code packs 24 logical qubits into 192 data qubits at distance 4, an encoding rate of 12.5%, higher than any other published code at this distance. Three independent sheet-codes share one chip; ancillas are shared, stabilizers are extracted in three sequential rounds, and the inactive sheets accumulate depolarizing noise during each round at rate 2p. We simulate the full circuit-level memory experiment with explicit CNOT cascades, depolarizing noise on every gate, and minimum-weight perfect matching decoding via PyMatching on Stim's detector error model. Threshold under the multiplex idle penalty falls between 0.4% and 0.5%, in agreement with the original construction paper. Distance scaling is sharp: the per-logical error rate suppresses by Λ(4→6) = 11.2 between consecutive even L at p = 0.001, and Λ(6→8) = 7.8. At L = 8 the [[1536, 48, 8]] code achieves a per-logical error rate of 5.9 × 10⁻⁵, more than an order of magnitude below the physical rate, on a 48-logical-qubit memory. These suppression factors, measured in simulation deeply sub-threshold, are over five times those recently reported on noisy hardware on a single-logical surface-code memory; an apples-to-apples comparison at matched operating point requires either future hardware experiments on this code or a surface-code simulation at the same deeply sub-threshold operating point and is not made here. The natural hardware target is the L = 6 instance: [[648, 36, 6]] encodes 36 logical qubits at distance 6 in 864 physical qubits, fitting Atom Computing's 1180-qubit Phoenix processor and exceeding every prior multi-logical hardware demonstration in distance and logical-qubit count. The L = 4 instance overlaps with Atom Computing and Microsoft's 24-logical [[4, 2, 2]] demonstration, providing a calibration point at quadrupled distance (d = 4 vs d = 2) and full error correction in place of error detection.
Abstract We provide a circuit-level numerical validation of the three-sheet time-multiplexed FCC sheet code, a quantum low-density parity-check (qLDPC) construction with parameters [[3L 3 , 6L, L]] derived from the three triad sheets of the face-centered cubic lattice. At L = 4 the code packs 24 logical qubits into 192 data qubits at distance 4, an encoding rate of 12.5%, higher than any other published code at this distance. Three independent sheet-codes share one chip; ancillas are shared, stabilizers are extracted in three sequential rounds, and the inactive sheets accumulate depolarizing noise during each round at rate 2p. We simulate the full circuit-level memory experiment with explicit CNOT cascades, depolarizing noise on every gate, and minimum-weight perfect matching decoding via PyMatching on Stim's detector error model. Threshold under the multiplex idle penalty falls between 0.4% and 0.5%, in agreement with the original construction paper. Distance scaling is sharp: the per-logical error rate suppresses by Λ(4→6) = 11.2 between consecutive even L at p = 0.001, and Λ(6→8) = 7.8. At L = 8 the [[1536, 48, 8]] code achieves a per-logical error rate of 5.9 × 10⁻⁵, more than an order of magnitude below the physical rate, on a 48-logical-qubit memory. These suppression factors, measured in simulation deeply sub-threshold, are over five times those recently reported on noisy hardware on a single-logical surface-code memory; an apples-to-apples comparison at matched operating point requires either future hardware experiments on this code or a surface-code simulation at the same deeply sub-threshold operating point and is not made here. The natural hardware target is the L = 6 instance: [[648, 36, 6]] encodes 36 logical qubits at distance 6 in 864 physical qubits, fitting Atom Computing's 1180-qubit Phoenix processor and exceeding every prior multi-logical hardware demonstration in distance and logical-qubit count. The L = 4 instance overlaps with Atom Computing and Microsoft's 24-logical [[4, 2, 2]] demonstration, providing a calibration point at quadrupled distance (d = 4 vs d = 2) and full error correction in place of error detection.
Abstract We present a CSS quantum error correcting code on the Face-Centered Cubic (FCC) lattice that combines surface-code-compatible K=4 connectivity with native inter-sheet logical gates between co-located CSS code blocks — a combination not previously achieved among well-studied codes. The construction has two parts. First, restricting the [[3L³, 2L³+2, 3]] FCC lattice code to a single triad sheet yields the sheet code with parameters [[L³, 2L, L]] at even L (or [[L³, L, L]] as a planar variant), uniform weight-4 stabilizers, and K=4 per-qubit connectivity. Three triad sheets share the FCC lattice geometry and can be deployed in one of three ways — monolithic 2D for small L, a three-layer stacked architecture for scalable deployment, or native 3D hardware — in each case encoding 6L logical qubits at distance L. Second, we introduce a fault-tolerant lattice surgery protocol that uses local FCC triangle measurements to implement joint Pauli measurements between logical qubits in different sheets. Each surgery operation adds O(L) two-qubit gates to the O(L³) per-round syndrome extraction cost. Under circuit-level depolarizing noise with MWPM decoding, the static memory threshold is p_th ≈ 0.63% and the surgery threshold is p_th ≈ 0.5%, both above the operating range of current quantum processors. Compared to surface code lattice surgery (also K=4, lattice surgery confined within a single patch), the sheet code provides 2L logicals per sheet at the same distance and connectivity; compared to bivariate bicycle codes (which target inter-block gates between physically separated modules at K=6 with long-range couplers), the sheet code achieves inter-sheet gates at K=4 with only short-range couplings between co-located sheets.
The three triad sheets of the face-centered cubic (FCC) lattice are edge-disjoint but share their vertex and octahedral-void ancilla positions. This paper quantifies what that sharing buys and what it costs. Running the three sheet codes in a three-round time-multiplexed cycle on one chip needs 4L^3 physical qubits, against 6L^3 for three separate blocks: a saving of exactly one third at every L, or 256 qubits instead of 384 at L = 4 and 864 instead of 1296 at L = 6. The price is measured here and is not small. Idle sheets accumulate depolarizing noise at rate 2p for two of every three rounds, and the circuit-level threshold falls from 1.13% +/- 0.08% to 0.86% +/- 0.06%, a factor of 1.3. Both figures are measured with the full FCC sheet-code circuit at L = 4, 6, 8, not with a surface-code proxy. Relation to the toric code. Each sheet decomposes exactly into L independent rotated 2D toric codes (Proposition 1), so the three-sheet code is 3L such codes sharing one ancilla set and one classical control pipeline. The sheets fail independently, and we say plainly that its memory behavior is the toric code's. We claim no encoding-rate advantage: at d = 4 the rate is 12.5%, which is identical to the rotated toric code [[16,2,4]], and the factor of two separating both from the rotated surface code is the usual periodic-boundary factor. Numerical results. Full circuit-level memory experiments in Stim with MWPM decoding, at L = 4, 6, 8 under the multiplex idle penalty. Sub-threshold suppression is Lambda(4->6) = 12.3 +/- 1.1 and Lambda(6->8) = 5.6 +/- 1.3 at p = 1e-3, on a memory carrying 24 to 48 logical qubits. These are the suppression factors of the underlying toric codes, confirmed to survive ancilla sharing and the idle penalty; we do not present them as evidence that this construction outperforms the surface code, and a matched-operating-point comparison is not made here. The L = 6 instance, [[648,36,6]] on 864 physical qubits, fits current neutral-atom processors.
The three triad sheets of the face-centered cubic (FCC) lattice, at even lattice size L, are edge-disjoint but share their vertex and octahedral-void ancilla positions. Running the three sheet codes in a three-round time-multiplexed cycle on one chip needs 4L3 physical qubits against 6L3 for three separate blocks, a saving of exactly one third at every L, for instance, 864 qubits instead of 1296 at L=6. The schedule is implemented explicitly, with all three sheets on one shared ancilla set; comparing it against the effective single-sheet model used for the parameter sweeps shows agreement to within 5% at L=4 and 2.2% at L=6. The cost of the saving is that each sheet idles for two of every three sub-rounds, and the finite-size crossing estimate of the circuit-level threshold falls from 1.13±0.08% to 0.86±0.06%: a factor of 1.3, that is a 24% relative reduction, or 0.27 percentage points. Sweeping the idle-to-gate noise ratio r over 0,1,2,4 gives estimates decreasing monotonically from 1.13% to 0.71%. The dual X-basis memory gives 0.78±0.05%, overlapping the Z value. All values are finite-size crossings at L=4,6,8 from the full FCC circuit, not asymptotic thresholds, and the quoted spreads are dominated by finite-size drift rather than statistical error. Each sheet decomposes exactly into L independent rotated 2D toric codes (Proposition 1), so the memory is the toric code’s and no encoding-rate advantage is claimed; at d=4, the rate equals the rotated toric code’s. In the simulated noise model, where no channel couples two sheets, the sheets fail independently. Sub-threshold suppression survives the sharing at Λ(4→6)=12.3±1.1 and Λ(6→8)=5.6±1.2 at p=10−3, on a memory carrying 24 to 48 logical qubits. Block-level failure probabilities are reported alongside, since they grow with the logical count: at L=6 and p=10−3, the 36-logical chip loses at least one logical qubit in about one experiment in sixty. The L=6 instance, [[648,36,6]], needs 864 physical qubits, within the nominal atom count of current neutral-atom processors; no implementability claim is made beyond that count.
We construct a three-dimensional Calderbank-Shor-Steane (CSS) stabilizer code on the Face-Centered Cubic (FCC) lattice. Physical qubits reside on the edges of the lattice (coordination K=12); X-stabilizers act on octahedral voids and Z-stabilizers on vertices, both with uniform weight 12. Computational verification confirms CSS validity (HXHZT=0 over GF(2)) and reveals k=2L3+2 logical qubits: k=130 at L=4 and k=434 at L=6, yielding encoding rates of 67.7% and 67.0% respectively. The minimum distance d=3 is proven exactly by exhaustive elimination of all weight-≤2 candidates combined with constructive weight-3 non-stabilizer codewords. The code parameters are [[192, 130, 3]] at L=4 and [[648, 434, 3]] at L=6. This rate is 24x higher than the cubic 3D toric code (2.8% at d=4), though at a lower distance (d=3 vs. d=4); the comparison is across different distances. The high rate originates in a structural surplus: the FCC lattice has 3L3 edges but only L3−2 independent stabilizer constraints, leaving k=2L3+2 logical degrees of freedom. We provide a minimum-weight perfect matching (MWPM) decoder adapted to the FCC geometry, demonstrate a 10x coding gain at p=0.001 (and 63x at p=0.0005), and discuss implications for fault-tolerant quantum computing on neutral-atom and photonic platforms.
Abstract The [[3𝐿 3 , 2𝐿 3 +2, 3]] CSS code on the Face-Centered Cubic (FCC) lattice achieves 67.7% encoding rate with weight-12 stabilizers, but its distance is capped at 𝑑 = 3 by weight-3 logical operators sitting at tetrahedral interstitial voids. These logicals carry a geometric fingerprint—one error per triad sheet, all three converging at a known void—that makes them detectable by a flag ancilla measuring the three-body parity 𝑍 𝑒𝑎 𝑍 𝑒𝑏 𝑍 𝑒𝑐 . The weight-3 logical flips this parity from +1 to −1; the stabilizer syndrome stays silent, but the flag sees it. Running 𝑅 independent flag rounds per syndrome cycle pushes the logical failure rate to 𝑝 3+𝑅 , so the effective distance is simply 𝑑eff = 3+𝑅—adjustable at runtime, with no changes to the code or its logical count. At 𝑅 = 4 the FCC+flags code achieves the same 𝑝 7 distance scaling as a distance-7 surface code, with a prefactor 𝑁void = 256 versus ∼ 10 for the surface code—the cost of encoding 130 logical qubits at 29.0% rate versus 1 logical qubit at 1.0%. An adaptive scheduling protocol cuts the flag overhead to under 0.1% of measurement cycles at realistic noise levels.
Despite significant progress on quantum low-density parity-check (qLDPC) codes, building qLDPC processors that are high-rate, high-throughput, hardware-friendly, and fast-to-decode remains a challenge. We introduce mitten codes, a family of qLDPC processor codes of encoding rate 20% and check weight 9, based on non-abelian groups. Their non-abelian structure evades distance bounds constraining abelian counterparts, allowing mitten codes to reach distance 18 and beyond with just a few hundred data qubits. The logical operators of a mitten code are related by the group action, yielding a modular, low-overhead logical toolkit: full Clifford operations follow from bridging two reusable seed surgery gadgets or from a single fixed extractor. Furthermore, qLDPC processors based on mitten codes support high-rate surgery that executes many logical measurements in parallel, and parallel magic-state injection into all logical qubits at once. Under circuit-level noise, with our fast decoder, the [[300,60,14]] mitten code achieves, without extrapolation, a block logical error rate of ∼10−11 per round at 0.1% physical error rate (PER), while the [[975,195,≤24]] code reaches ∼10−8 at 0.4% PER. Decoding 15 billion surgery experiments on the [[540,108,18]] code at 0.1% PER, we observe only two logical failures, demonstrating a qLDPC processor capable of running ∼1010 logical operations. Our decoder is compatible with sub-millisecond average latency per logical cycle, sufficient for real-time decoding on neutral atom hardware. Discovered by an end-to-end design pipeline built on sQetch, a distance estimator orders of magnitude faster than existing tools, and mapping efficiently onto near-term neutral atom and superconducting hardware, mitten codes open a practical path toward fault-tolerant quantum computation.