We present Limbo, a quantum multi-chip-first compiler that combines graph-partitioning and routing-first approaches to compilation. On a 24-cell benchmark against TKET, Limbo outperforms in every cell. On the hardest cell, it reduces cross-chip 2-qubit operations by 78% and compile time by a factor of 2735; the median compile-time ratio across the matrix is 119. Under a calibrated noise model whose intra-chip and cross-chip error rates draw from published experimental characterizations, Limbo's output reaches higher Hellinger fidelity than TKET on every informative cell. The pipeline first analyzes the structural topology of the input interaction graph and selects a matching cloud vendor. It then partitions the qubits across chips using multi-level hypergraph partitioning, sequences the residual cross-chip operations through an event scheduler driven by topological sorting, and transpiles each per-chip sub-circuit against the chosen device's coupling map and native gate set. In testing, we executed the pipeline end-to-end on Rigetti's Cepheus superconducting QPU and exercised the noise-aware routing path against the device's live qubit calibration data. Direct hardware validation of the multi-chip architectural claim itself remains, at this moment, gated on publicly cloud-accessible multi-chip quantum hardware. The open-source SDK is available at github.com/Jminding/Limbo-Quantum, with the compiler API (planned to be released in Fall 2026), project information, and the full benchmark matrix at limbosys.dev.
We present Limbo, a quantum multi-chip-first compiler that combines graph-partitioning and routing-first approaches to compilation. On a 24-cell benchmark against TKET, Limbo outperforms in every cell. On the hardest cell, it reduces cross-chip 2-qubit operations by 78% and compile time by a factor of 2735; the median compile-time ratio across the matrix is 119. Under a calibrated noise model whose intra-chip and cross-chip error rates draw from published experimental characterizations, Limbo's output reaches higher Hellinger fidelity than TKET on every informative cell. The pipeline first analyzes the structural topology of the input interaction graph and selects a matching cloud vendor. It then partitions the qubits across chips using multi-level hypergraph partitioning, sequences the residual cross-chip operations through an event scheduler driven by topological sorting, and transpiles each per-chip sub-circuit against the chosen device's coupling map and native gate set. In testing, we executed the pipeline end-to-end on Rigetti's Cepheus superconducting QPU and exercised the noise-aware routing path against the device's live qubit calibration data. Direct hardware validation of the multi-chip architectural claim itself remains, at this moment, gated on publicly cloud-accessible multi-chip quantum hardware. The open-source SDK is available at github.com/Jminding/Limbo-Quantum, with the compiler API (planned to be released in Fall 2026), project information, and the full benchmark matrix at limbosys.dev.
Modular quantum processors require a compiler to reason about two resources at the same time: local device connectivity and communication across QPUs. A mapping that is acceptable on a single coupling graph may be unsuitable for a modular machine if it creates excessive cross-QPU traffic, concentrates that traffic on a small number of interconnect links, or assigns many boundary qubits to a QPU with few communication ports. This paper presents QuPort, a Python and Qiskit-based compilation framework that studies this setting through an explicit three-level model: a weighted logical interaction graph, a directed physical coupling map, and an undirected QPU-level interconnect graph. The main partitioning method, TPCCAP, optimizes the implemented objective formed by weighted cut distance, communication-port overflow, and routed link-load congestion. The framework also includes heavy-edge clustering, balanced greedy partitioning, simulated-annealing refinement, communication-port-aware layout, extraction of remote two-qubit operations, local-only routing of per-QPU circuits, and topology-aware schedule estimation. The model is a compiler-level abstraction. It does not claim a calibrated hardware runtime or an implementation of a physical remote-gate protocol.
Abstract Distributed quantum computing requires compiler infrastructure capable of partitioning quantum circuits across multiple quantum processing units (QPUs) and synthesizing entanglement-assisted communication channels. Existing quantum compilers—including Qiskit, t|ket⟩, and BQSKit—operate on single-QPU execution models and lack native support for multi-QPU intermediate representations. We present DQC, an MLIR-based distributed quantum compiler featuring a custom dqc dialect and a five-pass compilation pipeline: (1) interaction-graph-based qubit partitioning with weighted edge-cut minimization, (2) TeleGate synthesis replacing cross-QPU gates with EPR pair allocations and quantum teleportation sequences, (3) greedy operation reordering for communication pre-staging, (4) MPI dialect lowering for distributed runtime abstraction, and (5) LLVM IR emission targeting a quantum simulation runtime. We evaluate DQC on a distributed 4-qubit Quantum Fourier Transform and four additional benchmarks, demonstrating correct multi-QPU execution with verified quantum state output. To our knowledge, DQC is the first open-source MLIR-native compiler infrastructure targeting distributed quantum circuit execution with end-to-end compilation from high-level quantum IR to executable LLVM IR.
Distributed quantum computing (DQC) seeks to scale beyond the limits of monolithic processors by interconnecting multiple quantum processing units (QPUs) through entanglement-based links. Realizing this vision requires the co-design of hardware and software across the domains of quantum networking, compilation, and scheduling, yet existing tools remain fragmented between monolithic circuit compilers and long-distance quantum network simulators. We present an open-source, topology-informed framework for the compilation and scheduling of distributed quantum programs. Given an input circuit and a description of the target network, the framework partitions and reconstructs the circuit into a distributed program that respects the specified inter- and intra-QPU topology, covers cross-QPU operations through gate and state teleportation, and schedules the result under either deterministic or stochastic entanglement-generation models. By accepting and emitting standard OpenQASM, the framework interoperates with existing monolithic toolchains, and its standardized module interfaces allow partitioning and scheduling strategies to be interchanged and benchmarked. Using this framework, we show that the best-performing compilation strategy varies across the tested circuits and network configurations, and that both network topology and intra-QPU connectivity substantially affect the entanglement cost of execution. These findings underscore the need for a co-design approach to distributed quantum computing, which our framework is designed to support.
Scalable quantum computing requires execution models that go beyond the capacity of a single quantum processing unit (QPU). Although current hardware platforms continue to increase in qubit count, large fault-tolerant applications require substantially more physical qubits, stronger connectivity, and lower effective error rates than a monolithic near-term device can provide. Multi-QPU and multi-core architectures therefore form an important route towards larger quantum systems. However, distributing a quantum computation introduces compiler and architecture constraints that do not arise in conventional classical distribution. A partitioned quantum circuit separates gates and qubits that may still be logically entangled or mutually dependent. The system must therefore provide quantum resources that support entanglement between the distributed circuit fragments, while each local subcircuit must remain executable on the hardware topology of its assigned QPU. In this thesis, graph states serve as the explicit interconnection resources for these nonlocal dependences: they encode the entanglement structure required to support teleportation-based operations across QPUs. This thesis studies scalable quantum execution as an architecture-driven compilation problem. It develops a staged framework in which distribution, graph-state-based interconnection, and interconnection robustness are treated as dependent compiler decisions. The framework addresses three connected questions: 1) how a large quantum circuit should be divided when the resulting subcircuits must match real QPU topologies; 2) how the graph states required to entangle and operate across the distributed circuit boundaries can be prepared efficiently on constrained hardware; and 3) how those graph-state resources can remain useful under the loss and fusion failures that arise during preparation and use. These questions define an execution path from a large logical circuit to distributed local workloads connected by explicit entanglement resources. The thesis makes three main technical contributions that instantiate this framework. 1) It introduces hardware-aware circuit cutting, which incorporates the relationship between subcircuit interaction graphs and target QPU topology into the partitioning objective. This stage produces distributed workloads and explicit cut boundaries where quantum entanglement must be supplied across QPUs. 2) It formulates graph-state preparation as the resource-generation stage for those boundaries and develops methods that reduce preparation depth and emitter usage by exploiting graph-state equivalence and divide-and-conquer construction. 3) It develops a robust graph-state interconnection scheme that uses tree-encoded fusion and spin-memory-assisted compilation to tolerate photon loss and probabilistic fusion failures, so that the graph state can serve as a reliable connection between distributed quantum program fragments.
As quantum computing systems continue to scale up and become more clustered, efficiently compiling user quantum programs into high-fidelity executable sequences on real hardware remains a key challenge for current quantum compilation systems. In this study, we introduce a system-software framework that integrates resource virtualization and hardware-aware compilation for real quantum computing processors, termed QSteed. QSteed virtualizes quantum processors through a 4-layer abstraction hierarchy comprising the real quantum processing unit (QPU), standard QPU (StdQPU), substructure of the QPU (SubQPU), and virtual QPU (VQPU). These abstractions, together with calibration data, device topology, and noise descriptors, are maintained in a dedicated database to enable unified and fine-grained management across superconducting quantum platforms. At run time, the modular compiler queries the database to match each incoming circuit with the most suitable VQPU, after which it confines layout, routing, gate resynthesis, and noise-adaptive optimizations to that virtual subregion. The complete stack has been deployed on the Quafu superconducting cluster, where experimental runs confirm the correctness of the virtualization model and the efficacy of the compiler without requiring modifications to user code. By integrating resource virtualization with a select-then-compile workflow, QSteed demonstrates a robust architecture for compiling programs on noisy superconducting processors. This architectural approach offers a promising path toward efficient compilation needs across various superconducting quantum computing platforms in the noisy intermediate-scale quantum era.
QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 100x faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA.