QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 100x faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA.
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arXiv admin note: substantial text overlap with arXiv:2308.07581
QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 100x faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA.
QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 10× faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA. Source code: http://github.com/pnnl/qasmtrans
The success of a quantum algorithm hinges on the ability to orchestrate a successful application induction. Detrimental overheads in mapping general quantum circuits to physically implementable routines can be the deciding factor between a successful and erroneous circuit induction. In QASMTrans, we focus on the problem of rapid circuit transpilation. Transpilation plays a crucial role in converting high-level, machine-agnostic circuits into machine-specific circuits constrained by physical topology and supported gate sets. The efficiency of transpilation continues to be a substantial bottleneck, especially when dealing with larger circuits requiring high degrees of inter-qubit interaction. QASMTrans is a high-performance C++ quantum transpiler framework that demonstrates 3-1111 × speedups compared to the commonly used Qiskit transpiler. We observe speedups on large dense circuits such as ‘uccsd_n24’ which require gates. QASMTrans successfully transpiles the aforementioned circuits in 7.9s, whilst Qiskit needs 502 seconds with optimization 1 and exceeds an hour of transpilation time with optimization 3. With QASMTrans providing transpiled circuits in a fraction of the time of prior transpilers, potential design space exploration, and heuristic-based transpiler design becomes substantially more tractable. QASMTrans is released at http://github.com/pnnl/qasmtrans.
The success of a quantum algorithm hinges on the ability to orchestrate a successful application induction. Detrimental overheads in mapping general quantum circuits to physically implementable routines can be the deciding factor between a successful and erroneous circuit induction. In QASMTrans, we focus on the problem of rapid circuit transpilation. Transpilation plays a crucial role in converting high-level, machine-agnostic circuits into machine-specific circuits constrained by physical topology and supported gate sets. The efficiency of transpilation continues to be a substantial bottleneck, especially when dealing with larger circuits requiring high degrees of inter-qubit interaction. QASMTrans is a high-performance C++ quantum transpiler framework that demonstrates up to 369X speedups compared to the commonly used Qiskit transpiler. We observe speedups on large dense circuits such as uccsd_n24 and qft_n320 which require O(10^6) gates. QASMTrans successfully transpiles the aforementioned circuits in 69s and 31s, whilst Qiskit exceeded an hour of transpilation time. With QASMTrans providing transpiled circuits in a fraction of the time of prior transpilers, potential design space exploration, and heuristic-based transpiler design becomes substantially more tractable. QASMTrans is released at http://github.com/pnnl/qasmtrans.
We present an analysis of quantum circuit fidelity across the full compilation stack, from high-level gate optimization through pulse-level control. We connect a C++ circuit optimizer to a per-gate Lindblad master-equation fidelity model whose decoherence channels are cross-validated against qiskit-dynamics and whose absolute predictions are benchmarked against execution on real hardware. Across a campaign of 4,452 experiment runs over 371 benchmark circuits, gate cancellation provides the dominant improvement (d=1.66, 72% of circuits improved), while circuit size and pulse duration are the strongest negative predictors of process fidelity (input gates r=−0.78; pulse duration r=−0.73, R2=0.53). A formal ablation study shows that pass ordering has no significant effect on two-qubit gate reduction (Kruskal--Wallis p=0.302). Comparing against Qiskit transpilation levels, we show that two-qubit gate count, not total gate count, is the hardware-relevant metric: our optimizer attains superior two-qubit reduction on structured circuits (87.8% on QFT, 100% on QAOA) whereas Qiskit's larger total-gate reduction is dominated by single-qubit (u3) consolidation. Finally, executing eight circuits on the IQM Resonance Garnet processor (8/8 jobs completed, job identifiers released) reveals that the model is a consistent upper bound: it preserves the relative difficulty ordering of circuits but overestimates absolute fidelity by a mean of 0.49, quantifying the error budget (crosstalk, leakage, readout) outside a T1/T2/depolarizing model. We release the framework, data, and scripts as open source.
Near-term intermediate-scale quantum (NISQ) devices are subject to considerable noise and short coherence time. Consequently, it is critical to minimize circuit execution latency and improve fidelity. Traditionally, each basis gate of a transpiled circuit is decoded into a fixed episode of the device control pulses. Recent studies investigate the merged pulse generation method for customized gates through quantum optimal control (QOC). In this work, we propose PAQOC, a novel QOC framework that can (i) exploit an augmented program-aware (APA) basis gate set for the tradeoff between compilation time and circuit performance, (ii) prune the search space based on a criticality-centric analytical model and experiment observations we learned from 150 benchmarks. Evaluations using seventeen applications show that PAQOC can achieve an average 54% reduction of the circuit latency, on average 43% reduction in compilation overhead, and a 1.27× improvement in fidelity. PAQOC is available on GitHub1.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.