A key challenge in scaling up rapid single flux quantum (RSFQ) circuits is managing the magnetic interference caused by their bias current distributions. This paper establishes a simulation-driven framework for optimizing RSFQ circuit bias current supply configurations using magnetic field uniformity as the primary metric. Through Ansys HFSS 3D electromagnetic simulations and subsequent data processing, we demonstrated that magnetic field uniformity—rather than absolute intensity—exhibits a stronger correlation with circuit success probability. We developed a quantitative scoring metric to systematically compare and select bias current configurations. Applying this scoring metric to an 8-bit central processing unit (CPU) series, we found that the fully functional version exhibits 6.0% lower magnetic field non-uniformity in the arithmetic logic unit (ALU) block compared to the non-functional one. The proposed method provides a viable approach to optimizing the layout of large-scale RSFQ circuit, specifically to the design of the bias current supply network.
A key challenge in scaling up rapid single flux quantum (RSFQ) circuits is managing the magnetic interference caused by their bias current distributions. This paper establishes a simulation-driven framework for optimizing RSFQ circuit bias current supply configurations using magnetic field uniformity as the primary metric. Through Ansys HFSS 3D electromagnetic simulations and subsequent data processing, we demonstrated that magnetic field uniformity—rather than absolute intensity—exhibits a stronger correlation with circuit success probability. We developed a quantitative scoring metric to systematically compare and select bias current configurations. Applying this scoring metric to an 8-bit central processing unit (CPU) series, we found that the fully functional version exhibits 6.0% lower magnetic field non-uniformity in the arithmetic logic unit (ALU) block compared to the non-functional one. The proposed method provides a viable approach to optimizing the layout of large-scale RSFQ circuit, specifically to the design of the bias current supply network.
The magnetic fields induced by the bias currents and the return currents flowing on a ground plane have a great influence on the performance of complex RSFQ circuits. Conventional approach applies equal negative bias currents to the ground contacts adjacent to the bias supply contacts to alleviate this problem, but this strategy may not be optimal when the power supply network is complex. We propose a new test approach to adjusting the negative bias currents independently. By changing the current distribution and thereby altering the spatial distribution of the magnetic field across the chip, this approach can make the circuit work, or make the circuit work more stably. Experimental validation on two 8-bit RSFQ CPUs demonstrated the approach's efficacy: redistributing negative currents restored functionality in a non-operational circuit and eliminated the intermittent failure in another. These results highlight the critical role of adjusting current distribution in overcoming magnetic interference, offering a practical solution for testing and optimizing the power supply of complex RSFQ circuits where conventional approach falls short.
Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.
High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under non-ideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes AC-to-DC converters, introducing area and complexity overhead. This work proposes an alternative method for applying AC biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for AC-to-DC converters. This approach also combines resistive DC biasing with inductive AC biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5%. The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.
Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.
Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.
Abstract As a member of the superconducting integrated circuit family, energy-efficient rapid single flux quantum (ERSFQ) circuit combines low-power consumption with high frequency, showing promise for application in high-energy efficient neuromorphic computing and traditional high-performance computing. Previous studies have demonstrated that there are typically two energy dissipation states in working ERSFQ circuits: energy-efficient SFQ state (E-state) and resistive-biased SFQ state (R-state). These states occur at different biasing current ranges, and the sum of the bias margin of these two states is close to the margin of rapid single flux quantum (RSFQ) circuits of the same design. For ultra-low-power applications, the bias current margin of the R-state must be excluded, leading to a substantially narrower bias margin in ERSFQ circuits than in their RSFQ counterparts. In our previous research, we proposed the feeding pulse method to increase the bias current margin by extending the lower boundary of the E-state through the injection of feeding pulses into the feeding Josephson transmission line (FJTL). In this study, we further investigated the current distribution mechanism in ERSFQ circuits and, based on this, proposed a method of optimizing design of the FJTL to redirect excess current to the FJTL, so as to expand the upper boundary of the E-state’s bias current margin. We tested an ERSFQ 8-bit shift register of the ERSFQ by applying methods proposed in this work together with the feeding pulses method proposed before. The results demonstrated that the bias current margin of the E-state expanded from (94%, 98%) to (56%, 116%), corresponding to a 14-times increase, with both the lower and upper boundary successfully extended. Our research addresses the issue of limited current bias margin in ERSFQ circuits during actual operation, providing a more robust ERSFQ technology for future applications in neural networks and high-performance computing.