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Large Scale Integration Issues in Superconducting Circuits

Supradeep Narayana

Published May 1, 2010• 1 citation
OpenAlex

Abstract

Superconducting digital logic technology, Rapid Single Flux Quantum (RSFQ), is established as the fastest technology in microelectronics based on Josephson junction devices. Technological challenges in large scale integration of superconductor circuits (RSFQ) namely: flux trapping, low power dissipation and multi-chip modules are addressed here. One of the main limitations of the integration of the RSFQ circuits is flux trapping, which arises due to the presence of residual magnetic field during transition of the circuit into superconducting state. Flux trapping is an unusual problem specific in only superconducting circuits. The effect of flux trapping in RSFQ circuits is studied, with a controlled 3-D magnetic field setup, quantitatively. Layout configuration with different moat patterns making RSFQ circuits tolerant to external magnetic field up-to 20mG was also developed. Low power issue was addressed by developing a new logic family. Power independent logic, an improved form of RSFQ logic, enables the circuits to operate only when needed and circuits can be switched off the remaining time; thereby eliminating static power consumption by retaining the logic state of the circuit. Flux trapping has also beeninvestigated in power independent cells. Current recycling is a technique to reduce the bias current applied for the operation of the RSFQ circuits. In this technique the cells are biased by serial connections. The reduction in supply current is proportional to number of blocks connected in series The effect of magnetic field on the operating margins of the current recycling circuits has also been studied. Operation of Multi-chip modules, one of the most viable solutions to develop large scale circuits, was demonstrated. Multi-chip modules with lithographically designed bumps is presented where data transmission rate between two superconducting chips exceed 100GHz. Finally, the development of the multi-modulator ADC for low noisefront end under-development is discussed.

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Superconducting digital logic technology, Rapid Single Flux Quantum (RSFQ), is established as the fastest technology in microelectronics based on Josephson junction devices. Technological challenges in large scale integration of superconductor circuits (RSFQ) namely: flux trapping, low power dissipation and multi-chip modules are addressed here. One of the main limitations of the integration of the RSFQ circuits is flux trapping, which arises due to the presence of residual magnetic field during transition of the circuit into superconducting state. Flux trapping is an unusual problem specific in only superconducting circuits. The effect of flux trapping in RSFQ circuits is studied, with a controlled 3-D magnetic field setup, quantitatively. Layout configuration with different moat patterns making RSFQ circuits tolerant to external magnetic field up-to 20mG was also developed. Low power issue was addressed by developing a new logic family. Power independent logic, an improved form of RSFQ logic, enables the circuits to operate only when needed and circuits can be switched off the remaining time; thereby eliminating static power consumption by retaining the logic state of the circuit. Flux trapping has also beeninvestigated in power independent cells. Current recycling is a technique to reduce the bias current applied for the operation of the RSFQ circuits. In this technique the cells are biased by serial connections. The reduction in supply current is proportional to number of blocks connected in series The effect of magnetic field on the operating margins of the current recycling circuits has also been studied. Operation of Multi-chip modules, one of the most viable solutions to develop large scale circuits, was demonstrated. Multi-chip modules with lithographically designed bumps is presented where data transmission rate between two superconducting chips exceed 100GHz. Finally, the development of the multi-modulator ADC for low noisefront end under-development is discussed.
Superconducting single flux quantum (SFQ) technology is well known for digital logic operations below 4.2 K, which are compatible with the Josephson junction qubit. Operation speed and signal sensitivity of circuits in SFQ are also sufficient to control qubits. Therefore, the SFQ circuit is a candidate technology for multiple qubit control. However, the self-heating effect of the SFQ circuit is a potential barrier to development of an SFQ-supported multiple qubit system because the qubit operating temperature is lower than the conventional 4.2 K. The multi-chip approach is a possible solution because the qubit chip can be thermally isolated from the SFQ circuitry. We report on recent progress in SFQ circuit and packaging technology for operation at sub-Kelvin temperatures. As for multi-chip module technology, a test sample of the multi-chip module shows good reliability of electrical connections between chips, and each solder bump has a bandwidth wide enough for signal transmission. We have designed lower power SFQ circuits for sub-Kelvin temperatures. The critical currents of Josephson junctions were scaled down, inductances were scaled up, and bias voltage was reduced to make power consumption lower. Based on our fabrication technology, critical current densities were optimized by considering trade-off relations between fabrication availability and operation speed. We successfully confirmed its correct operations at around 0.35 K. The combination of the multi-chip module and optimized SFQ circuits is very effective way of controlling qubit.
Rapid single flux quantum (RSFQ) electronics is based on the Josephson junction as an active switching element. In standard RSFQ circuits its switching energy is much lower than the static power consumption caused by the resistive current distribution network. Due to this thermal heating of the chip, the maximum number of junctions on a single chip is limited to about 1 million. The frequency-dependent contribution to power dissipation from junction switchings is only about 2 percent of the static one. This fact limits the direct construction of VLSI systems for high-performance computing as well as small-scale circuit applications in the vicinity of ultra-sensitive detectors or even quantum circuits. We present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents. We analyse the operation stability of simple digital circuits with 5 times smaller critical currents at 4.2 K. The combination of the reduced critical currents and inductive biasing can provide digital superconductive circuits with significantly reduced static power consumption.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
The article describes the activities aimed at bringing superconductive high-speed electronics towards maturity.Integrated circuits based on the effects in superconducting materials have become feasible for some years already.The main focus lies on the so-called Rapid Single-Flux-Quantum (RSFQ) electronics which allows the combination of high operation frequencies (well above 20 GHz) with very low energy consumption when logical states are changed.Thus, this circuit technology exhibits a promising potential for realising energy-efficient modules for signal processing and computing.Recently, a dedicated design infrastructure has been developed in Europe.Closely associated is a foundry for digital RSFQ integrated circuits so that the fabrication of integrated circuits is viable.In the contribution, the basic features of the RSFQ circuit design are addressed with special emphasis on implementation on the wafer scale.