Improved Sum-Min Decoding of Irregular LDPC Codes using Nonlinear Post-Processing

Juntan Zhang, M.P.C. Fossorier, Daqing Gu +1 more

Xu, Hua Hua, Wan  +7 more

Gottfried Lechner, Jossy Sayir

An analytical approach to determining the optimal post-processing function for the minimum operation in the SumMin algorithm, previously derived for regular Low-Density Parity-Check (LOPe) codes, is extended to irregular LDPC codes. The optimal post-processing expression for the irregular case varies from one check node to another as well as from one iteration to the next. For practical use, it is necessary to approximate this optimal function. Unlike for the regular case, where one could use a unique post-processing function throughout the decoding process without a loss of bit error performance, for irregular codes it is crucial to vary the post-processing from one iteration to the next in order to achieve good performance. Using this approach, a bit error performance of 0.15dS from the Sum-Product decoder was demonstrated, corresponding to a IdS improvement compared to the Sum-Min algorithm without post-processing.

양경철

Jinghu Chen, R. Michael Tanner, C. Jones +1 more

In this paper, we apply two improved min-sum algorithms, the normalized and offset min-sum algorithms, to the decoding of irregular LDPC codes. We show that the behavior of the two algorithms in decoding irregular LDPC codes is different from that in decoding regular LDPC codes, due to the existence of bit nodes of degree two. We analyze and give explanations to the difference, and propose approaches to improve the performance of the two algorithms.

Hua Xu, Wei Wan, Wei Wang +3 more

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units (GPUs). Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.