Emerging post-quantum cryptographic (PQC) algorithms demand execution speeds beyond the capabilities of conventional CMOS accelerators. This work introduces a hybrid CMOS–superconducting quantum co-processor architecture that synergizes room-temperature CMOS logic with a cryogenic superconducting quantum accelerator to achieve ultra-fast PQC operations. A segmented pipeline allocates key generation and parameter management to CMOS units, while time-critical modular arithmetic and lattice-based transformations execute on a superconducting quantum processing core. Co-design optimizes interconnect latency, cryogenic interface protocols, and error-mitigation routines. Prototype evaluations demonstrate a 10× throughput improvement for key encapsulation mechanisms and a 20× reduction in energy per operation compared to state-of-the-art CMOS-only PQC accelerators. The hybrid platform supports flexible algorithm updates and mitigates decoherence through dynamic qubit refresh and adaptive error correction. Results indicate feasibility for real-time secure communications in next-generation networks.
Emerging post-quantum cryptographic (PQC) algorithms demand execution speeds beyond the capabilities of conventional CMOS accelerators. This work introduces a hybrid CMOS–superconducting quantum co-processor architecture that synergizes room-temperature CMOS logic with a cryogenic superconducting quantum accelerator to achieve ultra-fast PQC operations. A segmented pipeline allocates key generation and parameter management to CMOS units, while time-critical modular arithmetic and lattice-based transformations execute on a superconducting quantum processing core. Co-design optimizes interconnect latency, cryogenic interface protocols, and error-mitigation routines. Prototype evaluations demonstrate a 10× throughput improvement for key encapsulation mechanisms and a 20× reduction in energy per operation compared to state-of-the-art CMOS-only PQC accelerators. The hybrid platform supports flexible algorithm updates and mitigates decoherence through dynamic qubit refresh and adaptive error correction. Results indicate feasibility for real-time secure communications in next-generation networks.
As superconducting and silicon-spin quantum processors scale from hundreds to thousands of physical qubits, the interconnect bottleneck between room-temperature classical electronics and mK cryogenic quantum processors poses a critical physical and architectural barrier. Low-latency control loops—essential for Quantum Error Correction (QED), fast reset protocols, and adaptive quantum algorithms—are strictly constrained by thermal load budgets, speed-of-light signal latency across thermal stages, and the bandwidth limits of coax lines. This paper presents a detailed architectural framework for next-generation quantum-classical interfaces. We investigate the transition from traditional, room-temperature arbitrary waveform generators (AWGs) connected via coaxial lines to co-integrated, cryo-CMOS, and single-flux-quantum (SFQ) digital-to-analog and digital signal processing control layers operating directly at the 4 K and 20 mK stages. We evaluate thermal transport, power dissipation, signal attenuation, and physical routing constraints, proposing a heterogeneous hybrid-control topology that satisfies latency budgets below 100 ns while remaining within the tight thermal limits of modern dilution refrigerators.
Scaling superconducting quantum computers toward thousands of control channels remains a difficult hardware problem. This requires reducing room-temperature-to-cryogenic interconnects and 4 K power while retaining channel-specific programmability. We develop a hybrid photonic/CMOS control architecture in which optical fibers distribute shared Gaussian and derivative pulse templates, while local cryogenic CMOS circuits provide event-rate amplitude programming, pulse blocking, hold-duration control, photodetection, and microwave upconversion. The architecture supports template-based XY/DRAG control and smooth-edged flat-top envelopes for two-qubit control through separate local signal paths. Compared with full-waveform Cryo-CMOS, it moves high-speed sampled-waveform generation out of each cryogenic channel. Compared with per-channel photonic waveform delivery, it retains a programmable endpoint after optical distribution for applying updated channel coefficients and control states. We evaluate the architecture using post-layout circuit simulations, optical and interconnect models, and system-level power scaling under a common 4 K output boundary. The modeled downlink power is below 1 mW per qubit-control channel at the thousand-channel scale, substantially below the normalized full-waveform Cryo-CMOS result and in the same range as the strict 50-ohm direct-detection WDM reference. Simulated I- and Q-path outputs are propagated through a five-level transmon model, while the simulated sample-and-hold output is evaluated in a coupled-transmon model. The tested single-qubit cases remain below the 10^-3 worst-state error reference, and the representative two-qubit result remains near the same scale after model-level calibration. These results support low-power photonic delivery with limited in-fridge programmability for template-compatible superconducting-qubit control.
Superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising technology for cryogenic applications (e.g., quantum computing, astronomy, metrology) thanks to its ultra-fast and low-energy characteristics. Therefore, recent efforts in SFQ-based computing have focused on developing fast and low-power SFQ processors for cryogenic applications. However, there still has been little progress toward a convincing SFQ processor design due to the critical performance challenges originating from its extremely deep pipeline. In this paper, we propose a super-fast and low-power in-order SFQ processor by tackling the challenges from the deep pipeline. First, we develop a minimal-depth SFQ processor pipeline with novel architecture-level ideas. Next, we conduct in-depth performance analyses and identify three real performance bottlenecks in the deeply pipelined SFQ processors (i.e., stall/flush logic, RAW stall, fetch unit). Finally, we propose SuperCore, our super-fast SFQ-based processor architecture, with three SFQ-friendly solutions that effectively resolve the identified bottlenecks. With our solutions applied, SuperCore achieves 11 times speed-up over the SFQ processor baseline. In addition, SuperCore achieves six times speed-up and consumes up to 193 times less power compared to in-order CMOS processors running at 4K.
Executing quantum circuits on superconducting platforms requires balancing the trade-off between gate errors and crosstalk. To address this, we introduce SurgeQ, a hardware-software co-design strategy consisting of a design phase and an execution phase, to achieve accelerated circuit execution and improve overall program fidelity. SurgeQ employs coupling-strengthened, faster two-qubit gates while mitigating their increased crosstalk through a tailored scheduling strategy. With detailed consideration of composite noise models, we establish a systematic evaluation pipeline to identify the optimal coupling strength. Evaluations on a comprehensive suite of real-world benchmarks show that SurgeQ generally achieves higher fidelity than up-to-date baselines, and remains effective in combating exponential fidelity decay, achieving up to a million-fold improvement in large-scale circuits.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Executing quantum circuits on superconducting platforms requires balancing the trade-off between gate errors and crosstalk. To address this, we introduce SurgeQ, a hardware-software co-design strategy consisting of a design phase and an execution phase, to achieve accelerated circuit execution and improve overall program fidelity. SurgeQ employs coupling-strengthened, faster two-qubit gates while mitigating their increased crosstalk through a tailored scheduling strategy. With detailed consideration of composite noise models, we establish a systematic evaluation pipeline to identify the optimal coupling strength. Evaluations on a comprehensive suite of real-world benchmarks show that SurgeQ generally achieves higher fidelity than up-to-date baselines, and remains effective in combating exponential fidelity decay, achieving up to a million-fold improvement in large-scale circuits.