IEICE Transactions on Electronics

Asynchronous Single Flux Quantum OR Gate with Input-Pattern-Insensitive Output Delay

Taisei YAHATA, Nobuyuki Yoshikawa, Yuki Yamanashi

Published Apr 22, 2026• 0 citations

Abstract

We propose an asynchronous OR gate based on the self-clocking method in single flux quantum (SFQ) circuits, which achieves output delay characteristics insensitive to input patterns. In a conventional self-clocking asynchronous OR gate, an imbalance in the number of SFQ pulses used for internal clock generation when generating an output pulse causes a significant input-pattern dependence in output delay. The proposed OR gate removes this imbalance by combining a self-clocking exclusive-OR gate and a self-clocking AND gate. We designed and evaluated the proposed OR gate assuming the use of the 10 kA/cm2 Nb fabrication process. At the standard bias voltage of 2.5 mV, the proposed OR gate exhibited no output delay difference among input patterns. The proposed OR gate has a more complex structure, leading to increased power consumption and gate area. In addition, 2N-input asynchronous OR circuits constructed using the proposed OR gate maintained stable operation as the number of logic stages increased, which could not be achieved using the conventional OR gate. By suppressing the output delay difference, the proposed OR gate enables stable operation of cascaded asynchronous OR structures with many logic stages.

DOI: 10.1587/transele.2025sep0001

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