Quantum Random Number Generators (QRNGs) serve as high entropy sources for Quantum Key Distribution (QKD) systems. The raw data from quantum sources however require post-processing to generate a nearly uniform distribution. This work presents a state-of-the-art implementation of the Toeplitz Strong Extractor on an FPGA, achieving a benchmark extraction speed of 26.57 Gbps. A detailed implementation flow of the post-processing on FPGA is presented along with the various execution speeds obtained based on different randomness extraction ratios. Raw data from an in-house phase noise-based QRNG is processed on the FPGA using the implementation and the output is validated via the NIST STS 2.1.2 statistical randomness tests suite.Quantum Random Number Generators (QRNGs) serve as high entropy sources for Quantum Key Distribution (QKD) systems. The raw data from quantum sources however require post-processing to generate a nearly uniform distribution. This work presents a state-of-the-art implementation of the Toeplitz Strong Extractor on an FPGA, achieving a benchmark extraction speed of 26.57 Gbps. A detailed implementation flow of the post-processing on FPGA is presented along with the various execution speeds obtained based on different randomness extraction ratios. Raw data from an in-house phase noise-based QRNG is processed on the FPGA using the implementation and the output is validated via the NIST STS 2.1.2 statistical randomness tests suite.

arXiv:2505.02868IEEE India Council International Subsections Conference (INDISCON)Aug 22, 20242 citations

Quantum Random Number Generators for Cryptography: Design and Evaluation

Puspak Pain, Arindam Sadhu, Kunal Das +1 more

Lecture notes in electrical engineeringOct 10, 20215 citations

Seed Renewable Parallel and Real-Time Toeplitz Post-Processing for QRNG

Fading Lin, Wenbo Ge, Zhijie Song +4 more

As a universal-hashing function, Toeplitz hashing is migrated in QRNG from privacy amplification of QKD to execute information-theoretically provable true randomness extraction. Though random seed needed for constructing a Toeplitz matrix is longer than the output string, Toeplitz-hashing extractor is still much more favored in practical implementation of QRNG because its relative simple structure and parallel operation property compared to the other universal-hashing strong extractor, Trevisan's extractor, especially in the booming integration realization of randomness extractor via FPGA. But two origin issues have been put off for long in the random number post-processing in FPGA besides chasing speed: collision probability threaten owing to small matrix and security parameter growth due to seed reuse. In this work, seed update and collision probability are both paid close attention when realize real-time parallel post-processing of CV-QRNG, who has a pretty practical prospect as well as greatest demand on post-processing both because of whose wide detection bandwidth and multibit discretization. We propose a sub-seed generation scheme based on reading and writing between two levels of memories in FPGA, which effectively avoid the consumption of logic resources. One seeds pool is built in storage element of the FPGA and distinct random seed is chosen for each post-processing instance by a random selection process. And the seeds pool is swiftly updated via PCIe interface once security parameter reaches a pre-set threshold. Furthermore, by elaborate layout of Toeplitz matrixes and two-layer parallel pipeline algorithm with TDM designed delicately, four-channel parallel seed renewable Toeplitz post-processing with matrix of about ${\mathbf{1700}\mathbf {\, \times \, }\mathbf{2500}}$ is realized with a real-time random number yield of 11.3 Gbps in one medium-configuration FPGA. In order to guarantee the robustness of the hardware-based parallel Toeplitz post-processing, timing is optimized by register replication, global clock buffers and data cache. This investigation fills an obvious hole in randomness extraction and provides a referential technique for privacy amplification.As a universal-hashing function, Toeplitz hashing is migrated in QRNG from privacy amplification of QKD to execute information-theoretically provable true randomness extraction. Though random seed needed for constructing a Toeplitz matrix is longer than the output string, Toeplitz-hashing extractor is still much more favored in practical implementation of QRNG because its relative simple structure and parallel operation property compared to the other universal-hashing strong extractor, Trevisan's extractor, especially in the booming integration realization of randomness extractor via FPGA. But two origin issues have been put off for long in the random number post-processing in FPGA besides chasing speed: collision probability threaten owing to small matrix and security parameter growth due to seed reuse. In this work, seed update and collision probability are both paid close attention when realize real-time parallel post-processing of CV-QRNG, who has a pretty practical prospect as well as greatest demand on post-processing both because of whose wide detection bandwidth and multibit discretization. We propose a sub-seed generation scheme based on reading and writing between two levels of memories in FPGA, which effectively avoid the consumption of logic resources. One seeds pool is built in storage element of the FPGA and distinct random seed is chosen for each post-processing instance by a random selection process. And the seeds pool is swiftly updated via PCIe interface once security parameter reaches a pre-set threshold. Furthermore, by elaborate layout of Toeplitz matrixes and two-layer parallel pipeline algorithm with TDM designed delicately, four-channel parallel seed renewable Toeplitz post-processing with matrix of about${\mathbf{1700}\mathbf {\, \times \, }\mathbf{2500}}$is realized with a real-time random number yield of 11.3 Gbps in one medium-configuration FPGA. In order to guarantee the robustness of the hardware-based parallel Toeplitz post-processing, timing is optimized by register replication, global clock buffers and data cache. This investigation fills an obvious hole in randomness extraction and provides a referential technique for privacy amplification.

Journal of Lightwave TechnologyAug 19, 20247 citations

Ultra-fast Quantum Random Number Generator

Yicheng Shi

Jan 1, 20160 citations

{\mathbf{1700}\mathbf {\, \times \, }\mathbf{2500}}

is realized with a real-time random number yield of 11.3 Gbps in one medium-configuration FPGA. In order to guarantee the robustness of the hardware-based parallel Toeplitz post-processing, timing is optimized by register replication, global clock buffers and data cache. This investigation fills an obvious hole in randomness extraction and provides a referential technique for privacy amplification.