[EN] The rapid scaling of quantum processors in the NISQ era presents a significant challenge for software development: the increasing opacity of the compilation process. As algorithms are mapped onto complex hardware with hundreds or thousands of qubits, the transformation from a high-level logical description to a sequence of physical operations becomes a black box, hindering intuition, debugging, and the development of optimized compilation strategies. This thesis introduces Quvis, a novel visualization tool designed to address this challenge. Quvis provides an interactive environment to dissect the compilation pipeline by mapping logical circuit interactions onto a dynamic representation of the target processor’s physical qubit connectivity. Developed using a hybrid architecture combining React and Three.js, the tool effectively synchronizes user-driven controls with a real-time visualisation of the quantum hardware. The hardware topology is rendered using a force-directed layout algorithm to produce clear and intuitive spatial representations. The utility of Quvis is demonstrated through the analysis of state-of-the-art quantum circuits, such as the Quantum Fourier Transform (QFT). Furthermore, the performance of the visualization tool itself is benchmarked, evaluating the scalability of its layout algorithms and rendering frame rates on modern hardware. By offering a transparent and intuitive view into the compilation process, Quvis serves as a valuable didactic and investigative tool. It bridges a critical gap in the quantum software stack, empowering researchers and developers to better understand and optimize the interaction between quantum algorithms and noisy, intermediate-scale hardware.
[EN] The rapid scaling of quantum processors in the NISQ era presents a significant challenge for software development: the increasing opacity of the compilation process. As algorithms are mapped onto complex hardware with hundreds or thousands of qubits, the transformation from a high-level logical description to a sequence of physical operations becomes a black box, hindering intuition, debugging, and the development of optimized compilation strategies. This thesis introduces Quvis, a novel visualization tool designed to address this challenge. Quvis provides an interactive environment to dissect the compilation pipeline by mapping logical circuit interactions onto a dynamic representation of the target processor’s physical qubit connectivity. Developed using a hybrid architecture combining React and Three.js, the tool effectively synchronizes user-driven controls with a real-time visualisation of the quantum hardware. The hardware topology is rendered using a force-directed layout algorithm to produce clear and intuitive spatial representations. The utility of Quvis is demonstrated through the analysis of state-of-the-art quantum circuits, such as the Quantum Fourier Transform (QFT). Furthermore, the performance of the visualization tool itself is benchmarked, evaluating the scalability of its layout algorithms and rendering frame rates on modern hardware. By offering a transparent and intuitive view into the compilation process, Quvis serves as a valuable didactic and investigative tool. It bridges a critical gap in the quantum software stack, empowering researchers and developers to better understand and optimize the interaction between quantum algorithms and noisy, intermediate-scale hardware.
Quantum computing has entered a stage of increasing practicality. Many quantum hardware vendors such as IBM, Rigetti, Honeywell, and IonQ now enable experiments on real devices in the Noisy Intermediate-Scale Quantum (NISQ) era. These platforms show computational advantages in domains such as optimization, machine learning, and materials science. However, they remain limited by hardware noise and the absence of human-interpretable information. Existing visual metaphors, such as the Bloch Sphere for single-qubit states or circuit schematics for algorithm design, struggle to convey multi-qubit entanglement or measurement probabilities in ways accessible to human reasoning. Likewise, the rise of variational quantum circuits and quantum neural networks (QNNs) introduces new layers of opacity: how data are encoded into quantum states and how parameters evolve through training remain largely under-explored. These challenges motivate a need for visual explanation frameworks that unveil the invisible processes of quantum computing visible, interpretable, and reasonable.To address these challenges, this dissertation presents a coherent sequence of visual analytics systems that progressively enhance explainability across the hardware, state, circuit, and model layers of quantum computing. First, VACSEN supports noise-aware execution by visually correlating hardware fidelity metrics with compiled quantum circuits, allowing users to identify unstable qubits, track temporal noise evolution, and select optimal execution strategies. Second, VENUS introduces a geometric representation for quantum state visualization, combining right triangles and semicircles to jointly encode amplitude and probability information, thereby enabling intuitive exploration of superposition and entanglement beyond the traditional Bloch Sphere. Third, QuantumEyes extends interpretability to quantum circuit behavior, integrating coordinated views to reveal how quantum gates transform amplitudes and probabilities during algorithm execution (e.g., Grover’s search or the Quantum Fourier Transform). Finally, VIOLET applies visual explainability to quantum neural networks, bridging concepts from explainable AI and quantum computing. It visualizes the encoding of classical data into quantum states, tracks parameter dynamics during variational training, and exposes learned features and measurement distributions, establishing the first end-to-end system for understanding QNNs.Each system was designed through iterative co-design with quantum computing experts and evaluated through case studies, task analyses, and in-depth interviews involving researchers and practitioners from academia and industry. Across evaluations, participants reported that visualization significantly enhanced their ability to reason about noise effects, understand quantum-state evolution, and interpret the learning behavior of QNNs. These findings demonstrate that visualization not only accelerates analysis and debugging but also strengthens conceptual understanding and user trust in quantum computing. To sum up, this dissertation establishes visualization
The rapid progress quantum devices have made in recent years has led to the need for systems that bridge the gap between quantum algorithms and quantum hardware. To this purpose different full-stack quantum programming platforms have been developed, providing high level languages for expressing quantum algorithms and providing compilers for making those quantum algorithms executable on a given quantum device. OpenQL is one such a platform, with support for compiling a variety of quantum program inputs into a quantum circuit, ready to be executed on the targeted quantum hardware. OpenQL is an evolving tool in which new features are constantly added to improve its performance and extend its functionality. In order to enhance OpenQL and provide some extra support to the researchers using OpenQL for their experiments, a visualization tool with three main functionalities has been developed in this thesis project. First, a circuit visualizer, with support for both visualizing the circuit output of the OpenQL compiler as an abstract gate representation and a pulse representation, which has been made specifically for quantum hardware running on superconducting qubits. Secondly, a mapping graph visualizer, which allows displaying the logical to physical qubit mapping per program cycle. And lastly a qubit interaction graph generator, which shows the required interactions between qubits of a given quantum algorithm.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Despite Noisy Intermediate-Scale Quantum devices being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed to enable successful algorithm executions. Not so much attention has been paid to mapping and compilation implementations for spin-qubit quantum processors due to the scarce availability of experimental devices and their small sizes. However, based on their high scalability potential and their rapid progress it is timely to start exploring solutions on such devices. In this work, we discuss the unique mapping challenges of a scalable crossbar architecture with shared control and introduce SpinQ , the first native compilation framework for scalable spin-qubit architectures. At the core of SpinQ is the Integrated Strategy that addresses the unique operational constraints of the crossbar while considering compilation scalability and obtaining a O(n) computational complexity. To evaluate the performance of SpinQ on this novel architecture, we compiled a broad set of well-defined quantum circuits and performed an in-depth analysis based on multiple metrics such as gate overhead, depth overhead, and estimated success probability, which in turn allowed us to create unique mapping and architectural insights. Finally, we propose novel mapping techniques that could increase algorithm success rates on this architecture and potentially inspire further research on quantum circuit mapping for other scalable spin-qubit architectures.
Quantum computing promises computational speedups over classical approaches for certain problem classes; however, in near term quantum and classical hybrid workflows, the overall performance is often constrained by classical processing overhead. The time cost associated with circuit compilation, which includes gate decomposition, topology aware qubit mapping, and depth optimization, together with protocol level communication such as circuit transfer and measurement result exchange, frequently exceeds the actual quantum circuit execution time and has become a critical bottleneck to practical deployment. In this paper, we propose QPanda 3.0, a high performance quantum programming framework optimized to accelerate the classical compilation path that underpins NISQ era hybrid integration. Leveraging an optimized compilation pipeline, a custom binary instruction stream (OriginBIS), and hardware aware execution strategies, QPanda 3.0 achieves up to 86.9 × faster encoding and 35.6 × faster decoding than OpenQASM 2.0, as well as an average 10.7 × compilation speedup over Qiskit across the four evaluated connectivity topologies, with a peak speedup of 597 × for a 118-qubit W-state circuit on a square topology. These capabilities enable the development of scalable quantum algorithms across various domains, including finance, materials science, and combinatorial optimization, supporting both industrial deployment and cloud based execution in hybrid computing environments.