STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
Combinatorial optimization problems ubiquitously appear in AI applications, e.g. machine learning, operational planning, drug discovery, etc. Yet, their NP-hardness makes them notoriously difficult to solve on present computers. To address this problem, new hardware architectures [1, 4], called annealers, have emerged in recent years. Annealers exploit the fact that combinatorial optimization problems can be mapped to the ground state search of an Ising model, where the combination of N spins (σ- ∈ f-1}. x=1, ...,N) with lowest Ising energy represents the optimal solution to the problem (Fig. 7.3.1).
This research is concerned with an annealing processor for efficiently solving a combinatorial optimization problem.\nIn order to realize a smart society, optimization of people and thingssuch as transportation networks, power networks, human resource allocationand routes is indispensable. Many of these problems are called combinatorial optimization problems and are known as very important problems in modern society. However, it is known that the combinatorial optimization problem is NP-hard and it is difficult to efficiently solve it with a conventional Neumann computer.\nIn recent years, the miniaturization of the process of manufacturing computer chips is approaching the physical limit. Therefore, especially in the solution by the full search, the improvement in speed due to the calculation speed of the computer cannot be expected. From such a background, dedicated hardware capable of solving a combination optimization problem at high speed and with low power consumption has been attracting attention.\nThe annealing processor is a general-purpose combination optimization solver that utilizes the property that the ground state of the optimization problem expressed by using the Ising model and the optimal solution of the combination optimization problem match. The Ising model is a ferromagnetic model in statistical physics expressed by spins having an upward and downward state, spin-spin interactions occurring between the spins, and an external magnetic field acting on each spin. The Ising model can express a combinatorial optimization problem by expressing a control target and a cost using these parameters. The annealing processor updates the spin state while slowly lowering the temperature parameters based on simulated annealing,which is an optimization method learned from natural phenomena generally called annealing. Eventually, the spin will reach the ground state with a high probability and obtain the optimal solution.\nAnnealing processors are classified into two types, the nearest neighbor type and the fully connected type, depending on the shape of the Ising model simulated on the hardware. In the nearest neighbor type, the coupling between spins is limited to only between adjacent spins, and in the full coupling type, coupling exists between arbitrary spins. The nearest neighbor type realizes high parallel processing by reducing the data spin required by simulated annealing by reducing the proximity spin. In addition, since data transfer is limited to adjacent spins, the scalability is high. However, since the spin-to-spin interaction is sparse, there is a problem that the class of combinatorial optimization problems that can be dealt with is limited, or that the problem requires deformation processing to match the Ising model of hardware. The fully connected type can solve any class of problems as long as the number of spins permits, however it requires connections between arbitrary spins.Therefore, scalability is low. Because there there is a dependency on all spins,the number of spins that can be updated at one time is always limited to only one regardless of the total number of spins. Therefore, it takes time to converge to the ground state.\nIn this research, we propose a method of increasing the number of spins for this annealing processor by using (1) a spatially-expanded time-division processing mechanism architecture based on a loosely-coupled type, (2) An algorithm for applying a fully coupled Ising network to a more complex Ising network using the nearest neighbor Ising network and an annealing method that can be updated in parallel, (3)We conducted a study on the architecture of a fully coupled annealing processor for parallel updating annealing.\nAs described above, the research described in this paper contributes to the improvement of the efficiency of the annealing processor for solving the large-scale combinatorial optimization problem from both the fundamental algorithm and the hardware architecture. I hope that this research will solve the combinatorial optimization problem that is expected to increase in demand in the future and contribute to the development of human society.
ABSTRACT Spatial photonic Ising machines (SPIMs) offer a promising physical computing architecture for solving NP‐hard combinatorial optimization problems. However, when applied to models with sparse spin interactions, conventional SPIMs still employ a fully connected scheme, which demands digital preprocessing to decompose the interaction matrix and encode full spin interactions, leading to massive resource consumption on spatial light modulators (SLMs) when the spin size is large. Here, we propose and experimentally demonstrate a wavelength‐division multiplexing scheme to enable sparse spin interactions for SPIMs, where only the non‐zero spin interactions are encoded by SLMs, bypassing the need for preprocessing computation. Leveraging the non‐Von Neumann architecture of photonic computing, this method reduces the computational complexity of a single‐spin update in Metropolis–Hastings sampling from to . We successfully applied this system to solve the Max‐Cut problem across various sparse graphs, achieving a considerable probability of finding optimal or near‐optimal solutions, with performance comparable to classical simulated annealing. The proposed spatial encoding scheme requires linear resources scaling with the number of connections between spins, providing a highly scalable and energy‐efficient optical accelerator platform for large‐scale sparse combinatorial optimization.
Autonomous navigation serves as a versatile technology prominently used in logistics and transportation. The application of automatic guided vehicles has become pervasive within the realm of factory automation, as shown in Fig. 30.4.1. For such applications, path planning and collision avoidance are two main tasks. Both tasks are classified as combinatorial optimization problems (COPs), and finding their optimal solutions is time-consuming [1]. A COP can be mapped to an Ising model with spin couplings based on the nature of the problem. Annealing is then applied to find the solution by iteratively updating spins until the states of the spins reach the lowest energy (known as a Hamiltonian). Digital annealers [2] –[4] have been demonstrated to accelerate solving COPs with exponential complexity. Some designs [2] [3] only support small-scale COPs because of the limited number of spins. The other [4] can solve larger problems, while the problem complexity is still limited by their sparse spin connections. Mapping a COP onto an Ising model and vice versa is necessary for solving a specific problem, which is also not addressed in the previous hardware digital annealers.