Autonomous navigation serves as a versatile technology prominently used in logistics and transportation. The application of automatic guided vehicles has become pervasive within the realm of factory automation, as shown in Fig. 30.4.1. For such applications, path planning and collision avoidance are two main tasks. Both tasks are classified as combinatorial optimization problems (COPs), and finding their optimal solutions is time-consuming [1]. A COP can be mapped to an Ising model with spin couplings based on the nature of the problem. Annealing is then applied to find the solution by iteratively updating spins until the states of the spins reach the lowest energy (known as a Hamiltonian). Digital annealers [2] –[4] have been demonstrated to accelerate solving COPs with exponential complexity. Some designs [2] [3] only support small-scale COPs because of the limited number of spins. The other [4] can solve larger problems, while the problem complexity is still limited by their sparse spin connections. Mapping a COP onto an Ising model and vice versa is necessary for solving a specific problem, which is also not addressed in the previous hardware digital annealers.
Autonomous navigation serves as a versatile technology prominently used in logistics and transportation. The application of automatic guided vehicles has become pervasive within the realm of factory automation, as shown in Fig. 30.4.1. For such applications, path planning and collision avoidance are two main tasks. Both tasks are classified as combinatorial optimization problems (COPs), and finding their optimal solutions is time-consuming [1]. A COP can be mapped to an Ising model with spin couplings based on the nature of the problem. Annealing is then applied to find the solution by iteratively updating spins until the states of the spins reach the lowest energy (known as a Hamiltonian). Digital annealers [2] –[4] have been demonstrated to accelerate solving COPs with exponential complexity. Some designs [2] [3] only support small-scale COPs because of the limited number of spins. The other [4] can solve larger problems, while the problem complexity is still limited by their sparse spin connections. Mapping a COP onto an Ising model and vice versa is necessary for solving a specific problem, which is also not addressed in the previous hardware digital annealers.
This research is concerned with an annealing processor for efficiently solving a combinatorial optimization problem.\nIn order to realize a smart society, optimization of people and thingssuch as transportation networks, power networks, human resource allocationand routes is indispensable. Many of these problems are called combinatorial optimization problems and are known as very important problems in modern society. However, it is known that the combinatorial optimization problem is NP-hard and it is difficult to efficiently solve it with a conventional Neumann computer.\nIn recent years, the miniaturization of the process of manufacturing computer chips is approaching the physical limit. Therefore, especially in the solution by the full search, the improvement in speed due to the calculation speed of the computer cannot be expected. From such a background, dedicated hardware capable of solving a combination optimization problem at high speed and with low power consumption has been attracting attention.\nThe annealing processor is a general-purpose combination optimization solver that utilizes the property that the ground state of the optimization problem expressed by using the Ising model and the optimal solution of the combination optimization problem match. The Ising model is a ferromagnetic model in statistical physics expressed by spins having an upward and downward state, spin-spin interactions occurring between the spins, and an external magnetic field acting on each spin. The Ising model can express a combinatorial optimization problem by expressing a control target and a cost using these parameters. The annealing processor updates the spin state while slowly lowering the temperature parameters based on simulated annealing,which is an optimization method learned from natural phenomena generally called annealing. Eventually, the spin will reach the ground state with a high probability and obtain the optimal solution.\nAnnealing processors are classified into two types, the nearest neighbor type and the fully connected type, depending on the shape of the Ising model simulated on the hardware. In the nearest neighbor type, the coupling between spins is limited to only between adjacent spins, and in the full coupling type, coupling exists between arbitrary spins. The nearest neighbor type realizes high parallel processing by reducing the data spin required by simulated annealing by reducing the proximity spin. In addition, since data transfer is limited to adjacent spins, the scalability is high. However, since the spin-to-spin interaction is sparse, there is a problem that the class of combinatorial optimization problems that can be dealt with is limited, or that the problem requires deformation processing to match the Ising model of hardware. The fully connected type can solve any class of problems as long as the number of spins permits, however it requires connections between arbitrary spins.Therefore, scalability is low. Because there there is a dependency on all spins,the number of spins that can be updated at one time is always limited to only one regardless of the total number of spins. Therefore, it takes time to converge to the ground state.\nIn this research, we propose a method of increasing the number of spins for this annealing processor by using (1) a spatially-expanded time-division processing mechanism architecture based on a loosely-coupled type, (2) An algorithm for applying a fully coupled Ising network to a more complex Ising network using the nearest neighbor Ising network and an annealing method that can be updated in parallel, (3)We conducted a study on the architecture of a fully coupled annealing processor for parallel updating annealing.\nAs described above, the research described in this paper contributes to the improvement of the efficiency of the annealing processor for solving the large-scale combinatorial optimization problem from both the fundamental algorithm and the hardware architecture. I hope that this research will solve the combinatorial optimization problem that is expected to increase in demand in the future and contribute to the development of human society.
Combinatorial optimization problems ubiquitously appear in AI applications, e.g. machine learning, operational planning, drug discovery, etc. Yet, their NP-hardness makes them notoriously difficult to solve on present computers. To address this problem, new hardware architectures [1, 4], called annealers, have emerged in recent years. Annealers exploit the fact that combinatorial optimization problems can be mapped to the ground state search of an Ising model, where the combination of N spins (σ- ∈ f-1}. x=1, ...,N) with lowest Ising energy represents the optimal solution to the problem (Fig. 7.3.1).
The Ising annealing processor has emerged as a promising approach to accelerate the discovery of the optimal solutions for a wide range of combinatorial optimization problems (COPs), by mapping various COPs into a unified Ising model. However, fixed computational strategies and inflexible architectures make previous designs suffer from a low hardware resource utilization rate when the numbers of the total required and real-time flipped spins vary across different COPs and iteration steps. In this paper, a novel spin scale-aware self-adaptive Ising annealing processing architecture (AIAPA) is proposed to address this problem, with an adaptive computational strategy, a custom instruction set, multi-traffic mode routers, and a fully-pipelined computing array. It can dynamically adapt to the varying scenarios during the Ising annealing process to maximize the performance of limited hardware resources. Its prototype, supporting 65k fully-connected spins, is implemented on an FPGA platform, operates at a clock frequency of 188 MHz. The AIAPA achieves up to a 24.22 times faster annealing speed compared to the state-of-the-art FPGA design on the max-cut optimization problem while maintaining a high convergence accuracy.
Annealing processors that can quickly solve combinatorial optimization problems (COPs) are attracting attention. They solve COPs by converting them into spin-spin interactions and external fields of the Ising model. Annealing processors that use fully-coupled spin coupling can solve a wide range of COPs. However, it is difficult to execute parallel annealing in fully-coupled spin coupling because one spin is updated by referring to all the other spins. In this paper, we proposed multi-state pseudo annealing (MSPA), which is an annealing method for changing the spin value from a conventional binary to a multi state that takes into account intermediate states. In a software validation, we solved the Maxcut problem and the traveling salesman problem and confirmed that the proposed method improves the solution quality in parallel annealing compared with simulated annealing and pseudo annealing. In addition, we implemented MSPA on a field-programmable gate array as a 1024 -spin 16 -parallel system using a scalable structure. With the proposed system, we solved the Max-cut problem and confirmed that it achieves a 9.40 times faster solving speed and yields a 1% larger Max-cut value compared with the conventional parallelized annealing processors.
In the noisy intermediate-scale quantum (NISQ) era, annealing-based computing is emerging as a new type of high-performance computing (HPC) technology for solving computationally intractable combinatorial optimization problems (COPs). Inspired by thermal annealing in metallurgy, the cost function of a COP is encoded in an energy function (Hamiltonian), with its lowest energy state being searched using an annealer and finally transformed to the global or global approximate optimal solution to a target problem. We address the key technology underlying annealing-based methods along with an experimental study with a commercial digital annealer (DA). We hope to shed light on how industries could benefit from this emerging computing technology to explore the challenges and opportunities in the quantum computing age.
Although quantum computing is expected to supplant traditional computing in several application fields, its adoption is hampered by temperature and economic constraints. To overcome these hurdles, researchers have proposed complementary metal-oxide-semiconductor (CMOS) annealing circuits. These circuits draw inspiration from quantum computing algorithms such as quantum annealing and aim to achieve near-quantum benefits by leveraging traditional CMOS technologies. This paper introduces an Ising-model-based hardware architecture that can be applied to combinatorial optimization problems (COPs). With its ability to express quadratic unconstrained binary optimization (QUBO) formulations as polynomials, the Ising model facilitates the encapsulation of multiple solutions and mapping onto fully connected architecture. The proposed annealing accelerator utilizes traditional circuit technologies, including pseudo-random number generators (PRNGs), to realize the required algorithms. The chip proposed herein, implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, operates at 50 MHz and covers an area of $3.24{\mathrm{m}}{{\mathrm{m}}^2}$3.24mm2. Experimental results demonstrate the excellent performance of this annealing accelerator in terms of area and power consumption, indicating its promise for use in solving COPs rapidly.