Cryogenic CMOS design techniques for scaled quantum computing systems

Sudipto Chakraborty

Farhad Mafie

Neeraj kumar, Aijaz Mehdi Zaidi, Balwinder Raj +1 more

Edoardo Charbon A, Fabio Sebastiano, Masoud Babaie +1 more

Yanshu Guo, Qichun Liu, Tiefu Li +4 more

This brief presents a brief overview of cryogenic CMOS circuits for large-scale quantum computing, especially the cryogenic RF circuits from the functional blocks to system-level ASICs. To start with, the cryogenic CMOS device characteristics of the process nodes ranging from 180nm to 5nm are examined and compared. The cryogenic RF blocks including the LNA and VCO in the recent literature are then briefly reviewed, with highlights on the key design points. The evolution of state-of-the-art system-level quantum interface cryogenic circuits is given including the design requirements, top-level architectures, and design considerations. The future directions and trends are also briefly discussed, aiming to promote the integration level of quantum computing.

Sudipto Chakraborty, Rajiv Joshi

This article will review recent progress in cryogenic CMOS designs for future scaled quantum computing applications. After introducing the scaling challenges associated with qubit control and readout electronics operating at room temperature, approaches taken to date to cryogenic control electronics design will be discussed, focusing on the most recent relevant publications. Elements of ultra-low power circuit and system design approaches for cryogenic controllers in scaled CMOS nodes (40nm to 14nm) will be reviewed, including a discussion of current state-of-the art cryogenic controller performance and power efficiency. Note that leading designs, when operated as transmon qubit state controllers, have achieved gate error rates in the range of 10-4 to 10-3 achieving spurious free dynamic range (SFDR) of ~40dB while consuming 4-23mW of power per qubit under active control, with power efficiency strongly driven by the complexity of the digital processor integrated in the controller design. These demonstrations, while significant, are just the first steps toward achieving the performance, efficiency, and scalability that will be required for future systems. This review article will discuss fundamental tradeoffs in CMOS cryogenic designs in order to address the needs of future scaled quantum computing systems.