This brief presents a brief overview of cryogenic CMOS circuits for large-scale quantum computing, especially the cryogenic RF circuits from the functional blocks to system-level ASICs. To start with, the cryogenic CMOS device characteristics of the process nodes ranging from 180nm to 5nm are examined and compared. The cryogenic RF blocks including the LNA and VCO in the recent literature are then briefly reviewed, with highlights on the key design points. The evolution of state-of-the-art system-level quantum interface cryogenic circuits is given including the design requirements, top-level architectures, and design considerations. The future directions and trends are also briefly discussed, aiming to promote the integration level of quantum computing.
This brief presents a brief overview of cryogenic CMOS circuits for large-scale quantum computing, especially the cryogenic RF circuits from the functional blocks to system-level ASICs. To start with, the cryogenic CMOS device characteristics of the process nodes ranging from 180nm to 5nm are examined and compared. The cryogenic RF blocks including the LNA and VCO in the recent literature are then briefly reviewed, with highlights on the key design points. The evolution of state-of-the-art system-level quantum interface cryogenic circuits is given including the design requirements, top-level architectures, and design considerations. The future directions and trends are also briefly discussed, aiming to promote the integration level of quantum computing.
Quantum computing holds the potential to solve problems beyond the capabilities of classical computers. However, realizing practical large-scale quantum computers faces critical challenges, including the key bottleneck in wiring quantum processors operating at cryogenic temperatures to their room temperature control electronics. This article explores cryo-CMOS ICs as an enabling technology to circumvent such a wiring bottleneck. After reviewing the basics of quantum computing and the behavior of CMOS devices at cryogenic temperatures, the requirements for the interface electronics for superconducting and semiconductor qubits are discussed, and state-of-the-art cryo-CMOS circuit solutions are briefly described, including a few hints to other qubit platforms. Finally, the article concludes with an overview of future challenges to be addressed to realize the vision of cryo-CMOS technology as an enabler of large-scale quantum computers with practical applications.
Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <; 100mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.
A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3digitally controlled oscillator required to manipulate the state of qubits.
Quantum computing requires scalable, energyefficient control electronics at cryogenic temperatures. Cryogenic CMOS (cryo-CMOS) enables integration with quantum processors, operating below 4 K while leveraging advanced CMOS processes. This paper reviews cryo-CMOS circuits and systems developed from 2016 to 2025, covering device behavior, analog, mixedsignal, and digital circuits, and system-level integration for largescale quantum control. Multiple implementations are compared, highlighting trade-offs in power, noise, scalability, and temperature operation. Key trends include fully integrated Cryo-SoCs, hybrid CMOS-III-V technologies, and machine-learning-assisted calibration. Remaining challenges in modeling, energy dissipation, and thermal management are discussed, outlining a roadmap for nextgeneration cryo-CMOS quantum architectures.
This article will review recent progress in cryogenic CMOS designs for future scaled quantum computing applications. After introducing the scaling challenges associated with qubit control and readout electronics operating at room temperature, approaches taken to date to cryogenic control electronics design will be discussed, focusing on the most recent relevant publications. Elements of ultra-low power circuit and system design approaches for cryogenic controllers in scaled CMOS nodes (40nm to 14nm) will be reviewed, including a discussion of current state-of-the art cryogenic controller performance and power efficiency. Note that leading designs, when operated as transmon qubit state controllers, have achieved gate error rates in the range of 10-4 to 10-3 achieving spurious free dynamic range (SFDR) of ~40dB while consuming 4-23mW of power per qubit under active control, with power efficiency strongly driven by the complexity of the digital processor integrated in the controller design. These demonstrations, while significant, are just the first steps toward achieving the performance, efficiency, and scalability that will be required for future systems. This review article will discuss fundamental tradeoffs in CMOS cryogenic designs in order to address the needs of future scaled quantum computing systems.
Nowadays, quantum computers are attracting much interest. In current quantum computers, measurement instruments, which provide functions of controlling and reading out quantum bits (qubits), operate under room temperature, and the instruments and qubits are connected by cables. This means that many cables are required for large-scale quantum computers, which could cause scalability issue. To reduce such cables, various CMOS LSIs operating at cryogenic temperature have been proposed for controlling and reading out qubits. In this paper, I briefly introduce characteristics of transistor and passive devices, such as resistors, capacitors, and inductors, at cryogenic temperature. Then, I review the latest research on cryogenic CMOS circuits for quantum computers.