The decline of Dennard scaling [1] has driven unsustainable power consumption, motivating exploration of post- CMOS technologies. Among these, Josephson Junction (JJ) based Single Flux Quantum (SFQ) logic offers ultrafast switching (tens of GHz) [2], [3] and extremely low switching energy (on the order of$10^{-19}$J) [2], [4]. Even accounting for cooling, SFQ circuits can be up to$1000\times$more energy-efficient than CMOS [4], [5], making them an attractive candidate for post-Moore computing. However, SFQ circuit designs are limited by JJ density and thus building SFQ CPUs must be cognizant of this limitation. Due to various SFQ circuit design limitations, such as limited fan out and path balancing, building a SFQ CPU requires spending majority of the JJ budget on control logic. This work proposes Icy-Hot, a novel granular decoupling of the pipeline stages in an SFQ CPU design. Icy-Hot exploits the ultra-fast SFQ computation in the superconducting zone while minimizing the JJ usage for memory and control logic by executing those pipeline stages in existing CMOS technology at 77K. Our evaluation of the proposed design achieves around a 38% power benefit while consuming only about 220,000 JJs.
The decline of Dennard scaling [1] has driven unsustainable power consumption, motivating exploration of post- CMOS technologies. Among these, Josephson Junction (JJ) based Single Flux Quantum (SFQ) logic offers ultrafast switching (tens of GHz) [2], [3] and extremely low switching energy (on the order of10−19J) [2], [4]. Even accounting for cooling, SFQ circuits can be up to1000×more energy-efficient than CMOS [4], [5], making them an attractive candidate for post-Moore computing. However, SFQ circuit designs are limited by JJ density and thus building SFQ CPUs must be cognizant of this limitation. Due to various SFQ circuit design limitations, such as limited fan out and path balancing, building a SFQ CPU requires spending majority of the JJ budget on control logic. This work proposes Icy-Hot, a novel granular decoupling of the pipeline stages in an SFQ CPU design. Icy-Hot exploits the ultra-fast SFQ computation in the superconducting zone while minimizing the JJ usage for memory and control logic by executing those pipeline stages in existing CMOS technology at 77K. Our evaluation of the proposed design achieves around a 38% power benefit while consuming only about 220,000 JJs.
Introduction Single Flux Quantum (SFQ) superconducting technology offers major performance and energy advantages over CMOS as Dennard scaling wanes. Yet, SFQ CPUs face key challenges: the Josephson Junction (JJ) budget limits manufacturability, and the lack of dense on-chip memory restricts scalability. Control and memory structures dominate JJ usage, motivating new architectures that exploit SFQ strengths while mitigating its limitations. Methods We introduce Icy-Hot, a hybrid CPU architecture that splits computation across two cryogenic zones. The 4 K Icy Zone, implemented with SFQ logic, performs high-speed execution, while the 77 K Hot Zone, built with CMOS, handles fetch, decode, and control. Compiler-inserted metadata and compact SFQ memory structures—a Hot-Driven Register File and a shift-register-based Dependency Buffer—enable decoupled pipeline execution and reduced cross-zone communication. Results Cycle-accurate simulations and SFQ circuit synthesis demonstrate that Icy-Hot achieves a 38% total power improvement over a 77 K CMOS baseline while using only ≈220,000 JJs, an 8× reduction from naïve SFQ cores. Loop-intensive workloads with high operand reuse achieve up to 4.5× performance speedup due to efficient local execution in the Icy Zone. Discussion By co-optimizing cryogenic CMOS and SFQ circuits, Icy-Hot demonstrates a practical path toward scalable, energy-efficient superconducting processors. The design captures SFQ’s intrinsic efficiency while addressing memory and control bottlenecks, marking a foundational step toward general-purpose SFQ CPU architectures.
Design and manufacturing of superconductive electronics have been evolving over the past three decades with significant progress made in related fields. Rapid single flux quantum (RSFQ) logic circuits have become popular among superconductive logic families and its energy-efficient variants (ERSFQ and eSFQ) have shown promise as an ultra lowpower and high-speed circuit fabric. SFQ circuits have been demonstrated at tens of GHz with an energy consumption of an attojoule per gate. There are many differences between SFQ and conventional CMOS circuits. SFQ logic circuits are based on the manipulation of the quantized magnetic flux pulses. Most of the logic gates are sequential in nature requiring the clock to be distributed to every logic gate. SFQ logic gates have no gain and hence splitters are needed to drive multiple fanouts. Design and successful demonstration of a controllable superconducting switch and a compact reliable memory element have evaded researchers so far. This paper starts by describing key differences between SFQ logic and conventional CMOS and concludes by listing key challenges that must be overcome to achieve the very large scale integration of SFQ circuits and make the demonstration of a superconductive CPU a reality.
Superconducting computing using single flux quantum (SFQ) technology has been recognized as a promising post-Moore's law era technology thanks to its extremely low power and high performance.Therefore, many researchers have proposed various SFQbased circuits (e.g., ALU, register file) and architectures (e.g., NPU, CPU) to exploit the potential.However, due to the absence of a reliable and high-frequency clocking scheme, general SFQ circuits cannot operate at high frequencies, making all architectural efforts for high-performance SFQ computing ineffective.In this paper, we propose SuperSFQ, a new design methodology for SFQ hardware that unlocks the high-frequency potential of SFQ technology by co-designing the clocking scheme, circuitry, and architecture.First, we propose SuperClocking, a new clocking scheme that enables high frequency in general SFQ hardware.Second, we implement an SFQ-based synchronizer to realize the reliable operation of SuperClocking.Finally, we provide two architectural design guidelines and corresponding solutions to ensure the functional correctness of SuperClocking in general SFQ devices.By applying our clocking scheme, synchronizer, and guidelines to the latest general-purpose SFQ CPU, SuperSFQ achieves up to 62.5 times higher frequency and improves single-thread and multithread performance by 17 and 62.5 times, respectively, compared to conventional designs, with only 34.4% Josephson junction overhead.In addition, to demonstrate the generality of SuperSFQ, we apply SuperSFQ to 48 different benchmark circuits, achieving 88.5 times higher frequency compared to conventional designs, on average.
The digital circuits in a superconducting quantum computer must be cooled to cryogenic temperatures in a dilution refrigerator for control and information readout of the qubit information. Because the dilution refrigerator's heat capacity is limited, extremely low-power digital circuits are required. Single-flux-quantum (SFQ) circuits and Josephson photomultipliers (JPMs) are expected to serve as control and readout circuits for superconducting quantum computers. These circuits generate minimal heat, but further reductions in power consumption are required to make it possible to build larger, more scalable faulttolerant quantum computers (FTQC). In this paper, we propose a low-power and reliable peripheral circuit for JPM-based qubit readout utilizing an SFQ counter circuit. The counter performs majority voting across repeated readouts, significantly improving the reliability of the JPM readout process. Additionally, we quantitatively evaluate switching errors in SFQ circuits using Josephson junctions with low-critical current values. By integrating these circuit techniques and simulation results, we find that the proposed approach achieves a 90% reduction in power consumption while effectively suppressing the increase in readout error.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology,$2\phi $-JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel$2\phi $-JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These$2\phi $-JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
Superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising technology for cryogenic applications (e.g., quantum computing, astronomy, metrology) thanks to its ultra-fast and low-energy characteristics. Therefore, recent efforts in SFQ-based computing have focused on developing fast and low-power SFQ processors for cryogenic applications. However, there still has been little progress toward a convincing SFQ processor design due to the critical performance challenges originating from its extremely deep pipeline. In this paper, we propose a super-fast and low-power in-order SFQ processor by tackling the challenges from the deep pipeline. First, we develop a minimal-depth SFQ processor pipeline with novel architecture-level ideas. Next, we conduct in-depth performance analyses and identify three real performance bottlenecks in the deeply pipelined SFQ processors (i.e., stall/flush logic, RAW stall, fetch unit). Finally, we propose SuperCore, our super-fast SFQ-based processor architecture, with three SFQ-friendly solutions that effectively resolve the identified bottlenecks. With our solutions applied, SuperCore achieves 11 times speed-up over the SFQ processor baseline. In addition, SuperCore achieves six times speed-up and consumes up to 193 times less power compared to in-order CMOS processors running at 4K.