Introduction Single Flux Quantum (SFQ) superconducting technology offers major performance and energy advantages over CMOS as Dennard scaling wanes. Yet, SFQ CPUs face key challenges: the Josephson Junction (JJ) budget limits manufacturability, and the lack of dense on-chip memory restricts scalability. Control and memory structures dominate JJ usage, motivating new architectures that exploit SFQ strengths while mitigating its limitations. Methods We introduce Icy-Hot, a hybrid CPU architecture that splits computation across two cryogenic zones. The 4 K Icy Zone, implemented with SFQ logic, performs high-speed execution, while the 77 K Hot Zone, built with CMOS, handles fetch, decode, and control. Compiler-inserted metadata and compact SFQ memory structures—a Hot-Driven Register File and a shift-register-based Dependency Buffer—enable decoupled pipeline execution and reduced cross-zone communication. Results Cycle-accurate simulations and SFQ circuit synthesis demonstrate that Icy-Hot achieves a 38% total power improvement over a 77 K CMOS baseline while using only ≈220,000 JJs, an 8× reduction from naïve SFQ cores. Loop-intensive workloads with high operand reuse achieve up to 4.5× performance speedup due to efficient local execution in the Icy Zone. Discussion By co-optimizing cryogenic CMOS and SFQ circuits, Icy-Hot demonstrates a practical path toward scalable, energy-efficient superconducting processors. The design captures SFQ’s intrinsic efficiency while addressing memory and control bottlenecks, marking a foundational step toward general-purpose SFQ CPU architectures.
Introduction Single Flux Quantum (SFQ) superconducting technology offers major performance and energy advantages over CMOS as Dennard scaling wanes. Yet, SFQ CPUs face key challenges: the Josephson Junction (JJ) budget limits manufacturability, and the lack of dense on-chip memory restricts scalability. Control and memory structures dominate JJ usage, motivating new architectures that exploit SFQ strengths while mitigating its limitations. Methods We introduce Icy-Hot, a hybrid CPU architecture that splits computation across two cryogenic zones. The 4 K Icy Zone, implemented with SFQ logic, performs high-speed execution, while the 77 K Hot Zone, built with CMOS, handles fetch, decode, and control. Compiler-inserted metadata and compact SFQ memory structures—a Hot-Driven Register File and a shift-register-based Dependency Buffer—enable decoupled pipeline execution and reduced cross-zone communication. Results Cycle-accurate simulations and SFQ circuit synthesis demonstrate that Icy-Hot achieves a 38% total power improvement over a 77 K CMOS baseline while using only ≈220,000 JJs, an 8× reduction from naïve SFQ cores. Loop-intensive workloads with high operand reuse achieve up to 4.5× performance speedup due to efficient local execution in the Icy Zone. Discussion By co-optimizing cryogenic CMOS and SFQ circuits, Icy-Hot demonstrates a practical path toward scalable, energy-efficient superconducting processors. The design captures SFQ’s intrinsic efficiency while addressing memory and control bottlenecks, marking a foundational step toward general-purpose SFQ CPU architectures.
The decline of Dennard scaling [1] has driven unsustainable power consumption, motivating exploration of post- CMOS technologies. Among these, Josephson Junction (JJ) based Single Flux Quantum (SFQ) logic offers ultrafast switching (tens of GHz) [2], [3] and extremely low switching energy (on the order of10−19J) [2], [4]. Even accounting for cooling, SFQ circuits can be up to1000×more energy-efficient than CMOS [4], [5], making them an attractive candidate for post-Moore computing. However, SFQ circuit designs are limited by JJ density and thus building SFQ CPUs must be cognizant of this limitation. Due to various SFQ circuit design limitations, such as limited fan out and path balancing, building a SFQ CPU requires spending majority of the JJ budget on control logic. This work proposes Icy-Hot, a novel granular decoupling of the pipeline stages in an SFQ CPU design. Icy-Hot exploits the ultra-fast SFQ computation in the superconducting zone while minimizing the JJ usage for memory and control logic by executing those pipeline stages in existing CMOS technology at 77K. Our evaluation of the proposed design achieves around a 38% power benefit while consuming only about 220,000 JJs.
Superconducting computing using single flux quantum (SFQ) technology has been recognized as a promising post-Moore's law era technology thanks to its extremely low power and high performance.Therefore, many researchers have proposed various SFQbased circuits (e.g., ALU, register file) and architectures (e.g., NPU, CPU) to exploit the potential.However, due to the absence of a reliable and high-frequency clocking scheme, general SFQ circuits cannot operate at high frequencies, making all architectural efforts for high-performance SFQ computing ineffective.In this paper, we propose SuperSFQ, a new design methodology for SFQ hardware that unlocks the high-frequency potential of SFQ technology by co-designing the clocking scheme, circuitry, and architecture.First, we propose SuperClocking, a new clocking scheme that enables high frequency in general SFQ hardware.Second, we implement an SFQ-based synchronizer to realize the reliable operation of SuperClocking.Finally, we provide two architectural design guidelines and corresponding solutions to ensure the functional correctness of SuperClocking in general SFQ devices.By applying our clocking scheme, synchronizer, and guidelines to the latest general-purpose SFQ CPU, SuperSFQ achieves up to 62.5 times higher frequency and improves single-thread and multithread performance by 17 and 62.5 times, respectively, compared to conventional designs, with only 34.4% Josephson junction overhead.In addition, to demonstrate the generality of SuperSFQ, we apply SuperSFQ to 48 different benchmark circuits, achieving 88.5 times higher frequency compared to conventional designs, on average.
Superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising technology for cryogenic applications (e.g., quantum computing, astronomy, metrology) thanks to its ultra-fast and low-energy characteristics. Therefore, recent efforts in SFQ-based computing have focused on developing fast and low-power SFQ processors for cryogenic applications. However, there still has been little progress toward a convincing SFQ processor design due to the critical performance challenges originating from its extremely deep pipeline. In this paper, we propose a super-fast and low-power in-order SFQ processor by tackling the challenges from the deep pipeline. First, we develop a minimal-depth SFQ processor pipeline with novel architecture-level ideas. Next, we conduct in-depth performance analyses and identify three real performance bottlenecks in the deeply pipelined SFQ processors (i.e., stall/flush logic, RAW stall, fetch unit). Finally, we propose SuperCore, our super-fast SFQ-based processor architecture, with three SFQ-friendly solutions that effectively resolve the identified bottlenecks. With our solutions applied, SuperCore achieves 11 times speed-up over the SFQ processor baseline. In addition, SuperCore achieves six times speed-up and consumes up to 193 times less power compared to in-order CMOS processors running at 4K.
The control of cryogenic qubits in today’s super-conducting quantum computer prototypes presents significant scalability challenges due to the massive costs of generating/routing the analog control signals that need to be sent from a classical controller at room temperature to the quantum chip inside the dilution refrigerator. Thus, researchers in industry and academia have focused on designing in-fridge classical controllers in order to mitigate these challenges. Due to the maturity of CMOS logic, many industrial efforts (Microsoft, Intel) have focused on Cryo-CMOS as a near-term solution to design in-fridge classical controllers. Meanwhile, Supercon-ducting Single Flux Quantum (SFQ) is an alternative, less mature classical logic family proposed for large-scale in-fridge controllers. SFQ logic has the potential to maximize scalability thanks to its ultra-high speed and very low power consumption. However, architecture design for SFQ logic poses challenges due to its unconventional pulse-driven nature and lack of dense memory and logic. Thus, research at the architecture level is essential to guide architects to design SFQ-based classical controllers for large-scale quantum machines.In this paper, we present DigiQ, the first system-level design of a Noisy Intermediate Scale Quantum (NISQ)-friendly SFQ-based classical controller. We perform a design space exploration of SFQ-based controllers and co-design the quantum gate decompositions and SFQ-based implementation of those decompositions to find an optimal SFQ-friendly design point that trades area and power for latency and control while ensuring good quantum algorithmic performance. Our co-design results in a single instruction, multiple data (SIMD) controller architecture, which has high scalability, but imposes new challenges on the calibration of control pulses. We present software-level solutions to address these challenges, which if unaddressed would degrade quantum circuit fidelity given the imperfections of qubit hardware.To validate and characterize DigiQ, we first implement it using hardware description languages and synthesize it using state-of-the-art/validated SFQ synthesis tools. Our synthesis results show that DigiQ can operate within the tight power and area budget of dilution refrigerators at >42,000-qubit scales. Second, we confirm the effectiveness of DigiQ in running quantum algorithms by modeling the execution time and fidelity of a variety of NISQ applications. We hope that the promising results of this paper motivate experimentalists to further explore SFQ-based quantum controllers to realize large-scale quantum machines with maximized scalability.
This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm −2 , 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s −1 , both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.
CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.