Abstract Current quantum software architectures rely on the Born rule as a universal axiom for converting quantum states into measurement statistics. In practice, near-term (NISQ) processors operate as noisy, driven open systems, where equilibrium assumptions are not guaranteed and systematic deviations can bias algorithmic outcomes. We introduce a Modular Software Stack for Quantum Systems in which the Born rule is reinterpreted as an operational equilibrium fixed point associated with modular (KMS) balance. A modular diagnostics layer, based on the Modular Imbalance Score (MIS), identifies reproducible nonequilibrium structure directly from experimentally reconstructed reduced states and applies a universal, normalization-preserving correction when warranted. We validate the framework on superconducting quantum hardware, 1 demonstrating statistically significant modular imbalance and automated model selection via information criteria. As an algorithmic application, we show that modular-aware post-processing improves the accuracy of a variational quantum eigensolver (VQE) on IBM Quantum devices, outperforming standard Born-based estimation and zero-noise extrapolation in nonequilibrium measurement regimes. Together, these results establish modular diagnostics as a physically grounded, falsifi-able, and scalable software layer that bridges nonequilibrium thermodynamics and practical quantum computing.
Abstract Current quantum software architectures rely on the Born rule as a universal axiom for converting quantum states into measurement statistics. In practice, near-term (NISQ) processors operate as noisy, driven open systems, where equilibrium assumptions are not guaranteed and systematic deviations can bias algorithmic outcomes. We introduce a Modular Software Stack for Quantum Systems in which the Born rule is reinterpreted as an operational equilibrium fixed point associated with modular (KMS) balance. A modular diagnostics layer, based on the Modular Imbalance Score (MIS), identifies reproducible nonequilibrium structure directly from experimentally reconstructed reduced states and applies a universal, normalization-preserving correction when warranted. We validate the framework on superconducting quantum hardware, 1 demonstrating statistically significant modular imbalance and automated model selection via information criteria. As an algorithmic application, we show that modular-aware post-processing improves the accuracy of a variational quantum eigensolver (VQE) on IBM Quantum devices, outperforming standard Born-based estimation and zero-noise extrapolation in nonequilibrium measurement regimes. Together, these results establish modular diagnostics as a physically grounded, falsifi-able, and scalable software layer that bridges nonequilibrium thermodynamics and practical quantum computing.
The progress in developing quantum hardware with functional quantum processors integrating tens of noisy qubits, together with the availability of near-term quantum algorithms has led to the release of the first quantum computers. These quantum computing systems already integrate different software and hardware components of the so-called “full-stack”, bridging quantum applications to quantum devices. In this paper, we will provide an overview on current full-stack quantum computing systems. We will emphasize the need for tight co-design among adjacent layers as well as vertical cross-layer design to extract the most from noisy intermediate-scale quantum (NISQ) processors which are both error-prone and severely constrained in resources. As an example of co-design, we will focus on the development of hardware-aware and algorithm-driven compilation techniques.
The maturation of quantum computing from theoretical physics to engineering reality presents a complex landscape for stakeholders navigating the transition from Noisy Intermediate-Scale Quantum (NISQ) devices toward Fault-Tolerant Quantum Computation (FTQC). This report provides a comprehensive, technically rigorous analysis of the current quantum ecosystem, examining the hardware mosaic of leading qubit modalities—superconducting circuits, trapped ions, neutral atoms, and silicon spin qubits—and evaluating them against operational metrics, including coherence times, gate fidelities, and cryogenic infrastructure requirements. We dissect the full software stack, differentiating the near-term utility of error mitigation techniques such as Zero-Noise Extrapolation (ZNE) from the long-term necessity of Quantum Error Correction (QEC) and the milestone of logical qubit break-even. The analysis benchmarks hybrid algorithms (VQE, QAOA) and circuit knitting strategies against current cloud-accessible hardware performance, while also addressing the imminent non-computational impact of PostQuantum Cryptography (PQC) migration. Experimental data synthesised from leading vendor roadmaps and pre-print literature indicate that superconducting platforms currently lead in gate speed (nanosecond regime) but face crosstalk scaling challenges beyond 1,000 qubits. In contrast, trapped-ion and neutral-atom architectures demonstrate superior connectivity and coherence. The report concludes with a grounded, evidence-based five-year projection, identifying high-value vertical use cases in pharmaceuticals and finance, and providing a strategic framework for enterprises to separate quantum hype from tangible commercial opportunity. Future research directions include the realisation of low-overhead Quantum LDPC codes and the development of modular photonic interconnects to scale beyond single-chip architectures.
The transition from noisy intermediate-scale quantum (NISQ) processors to large-scale fault-tolerant machines requires more than incremental improvements in physical qubit fidelity. While advances in quantum error correction (QEC) theory continue to lower the theoretical overhead of quantum computing, much of this research remains abstracted from the physical realities of qubit implementations. This disconnect often results in hardware-agnostic designs that are inefficient or impractical to build. In this dissertation, I identify three primary gaps between theoretical QEC research and practical hardware: (1) the high levels of noise and temporal instability in experimental devices that impede scalable QEC; (2) the prohibitively large qubit and time costs of useful algorithms, driven largely by the limitations of the standard surface code; and (3) the failure of current resource estimates to account for hardware-level constraints, such as limited connectivity and the complexity of implementing non-local operations. To bridge these gaps, I propose a holistic, cross-stack approach where the error correction protocols and the physical hardware are designed in concert. By developing realistic device models and hardware-aware solutions at the lowest levels of the software stack, we can accelerate the path toward functional fault-tolerance. I present my work across three research thrusts: first, leveraging codesign to mitigate hardware-specific noise and reduce physical error rates; second, developing software tools for fault-tolerant quantum computers to reduce the space-time overhead of the QEC layer; and third, proposing two novel hardware-aware QEC architectures that provide practical, high-performance routes to scalable quantum computation.
The advances in quantum hardware with functional quantum processors integrating tens of noisy qubits, together with the availability of near-term quantum algorithms have allowed the development of the so-called full-stacks that bridge quantum applications with quantum devices. In this talk, we will provide an overview of the different layers of the quantum computing full-stack, with emphasis on the software ones that include the compilation of quantum algorithms. We will then discuss the need for optimal physical-aware and algorithm-driven compilation techniques in the midst of the NISQ (Noisy Intermediate-scale quantum) era. We will also focus on key principles for architecting quantum computers such as codesign, optimization and benchmarking and illustrate how the use of structured design space exploration methodologies could help towards the development of a cross-layer codesign framework for full-stack quantum computing systems. Finally, we will talk about the scalability of quantum computing systems, which is one of the main challenges the quantum computing community is currently facing.
As quantum computing systems continue to scale up and become more clustered, efficiently compiling user quantum programs into high-fidelity executable sequences on real hardware remains a key challenge for current quantum compilation systems. In this study, we introduce a system-software framework that integrates resource virtualization and hardware-aware compilation for real quantum computing processors, termed QSteed. QSteed virtualizes quantum processors through a 4-layer abstraction hierarchy comprising the real quantum processing unit (QPU), standard QPU (StdQPU), substructure of the QPU (SubQPU), and virtual QPU (VQPU). These abstractions, together with calibration data, device topology, and noise descriptors, are maintained in a dedicated database to enable unified and fine-grained management across superconducting quantum platforms. At run time, the modular compiler queries the database to match each incoming circuit with the most suitable VQPU, after which it confines layout, routing, gate resynthesis, and noise-adaptive optimizations to that virtual subregion. The complete stack has been deployed on the Quafu superconducting cluster, where experimental runs confirm the correctness of the virtualization model and the efficacy of the compiler without requiring modifications to user code. By integrating resource virtualization with a select-then-compile workflow, QSteed demonstrates a robust architecture for compiling programs on noisy superconducting processors. This architectural approach offers a promising path toward efficient compilation needs across various superconducting quantum computing platforms in the noisy intermediate-scale quantum era.
Quantum computing has transitioned from a theoretical curiosity to an emerging technological paradigm with demonstrable computational advantages in specific problem domains. This paper presents a comprehensive review of current advances in quantum computing hardware, software, and near-term applications within the Noisy Intermediate-Scale Quantum (NISQ) era. We examine the architectural evolution of leading quantum platforms, including superconducting, trapped-ion, and photonic systems, analyzing their qubit counts, gate fidelities, and coherence times. The paper evaluates key quantum algorithms Shor's factoring algorithm [1], Grover's search algorithm [2], the Variational Quantum Eigensolver (VQE) [3], and the Quantum Approximate Optimization Algorithm (QAOA) [4] in the context of their practical applicability to real-world problems. We further discuss the milestone of quantum computational advantage demonstrated by Google's Sycamore processor [5] and IBM's ambitious hardware roadmap toward fault-tolerant quantum computing [6]. Our analysis reveals that while universal fault-tolerant quantum computing remains a long-term objective, NISQ-era devices are already yielding valuable results in quantum chemistry simulation, combinatorial optimization, and quantum machine learning. We conclude by identifying the critical challenges—error correction, scalability, and algorithm design that must be addressed to realize the full potential of quantum computing.