This thesis investigates design considerations and topologies for spin-qubit control circuits integrated with qubits and readout circuits into one- and two-lane quantum processor test vehicles in a production 22-nm FDSOI process. The control circuits produce millimeter-wave pulses through direct modulation of an externally generated carrier in the DC-to-70-GHz and 140-to-160-GHz frequency ranges. At 2 K, one design featuring a shunt-series-shunt switch achieves 31.1 dB to 77.7 dB of on/off isolation from DC to 27 GHz, while another featuring a distributed switch achieves > 30.2 dB of on/off isolation at 2-46 GHz and 50-70 GHz. The standalone distributed switch shows > 34 dB of on/off isolation over 40-218 GHz at 295 K. These measurements demonstrate not only the possibility of minimizing qubit idling errors with the adopted switch topologies, but also the feasibility of the proposed elevated-temperature (1-7 K) monolithic quantum processor and methodology for designing cryogenic control circuits.
This thesis investigates design considerations and topologies for spin-qubit control circuits integrated with qubits and readout circuits into one- and two-lane quantum processor test vehicles in a production 22-nm FDSOI process. The control circuits produce millimeter-wave pulses through direct modulation of an externally generated carrier in the DC-to-70-GHz and 140-to-160-GHz frequency ranges. At 2 K, one design featuring a shunt-series-shunt switch achieves 31.1 dB to 77.7 dB of on/off isolation from DC to 27 GHz, while another featuring a distributed switch achieves > 30.2 dB of on/off isolation at 2-46 GHz and 50-70 GHz. The standalone distributed switch shows > 34 dB of on/off isolation over 40-218 GHz at 295 K. These measurements demonstrate not only the possibility of minimizing qubit idling errors with the adopted switch topologies, but also the feasibility of the proposed elevated-temperature (1-7 K) monolithic quantum processor and methodology for designing cryogenic control circuits.
This thesis proposes a pathway to realizing large-scale quantum computing integrated circuits based on the monolithic integration of high-temperature (1–4 K) semiconductor qubits with their associated control and readout circuitry. High-frequency device characterization was performed on production 22-nm FDSOI technology at room and cryogenic temperatures (down to 3.3 K) to inform a cryogenic circuit design methodology in the absence of low-temperature device models. The methodology was demonstrated with a TIA qubit-readout chain that was, for the first time, monolithically integrated with electron and hole quantum dot structures. The prospects of FDSOI SiGe BiCMOS technology would enable similar integration with higher performance HBT devices. As a first step, design of a 240-GHz direct conversion I-Q receiver is showcased in 55-nm SiGe BiCMOS, intended for frequency-division multiplexed readout of many qubits. The measured IF-bandwidth of 59 GHz makes it suitable for high data-rate communication and large-scale quantum processors.
This work presents a collection of circuits to promote the development of a large-scale monolithicintegrated quantum processor in 22 nm FDSOI CMOS technology. These circuits are: a feedback circuit for automatically biasing CMOS inverter-based circuits, an LC resonator for qubit readout reflectometry and a digitally-controlled oscillator (DCO) for generating qubit spin manipulation pulses. The auto-biasing feedback circuit exploits the backgate terminal in FDSOI transistors to optimally bias CMOS inverter-based circuits at cryogenic temperatures. The LC resonator uses a sub-minimum-sized transistor with 50 nm width to demonstrate the detection of capacitance changes as small as 20 aF in a reflectometry experiment, which is analogous to the detection of a quantum state measurement. The DCO uses the same 50 nm device to achieve a fine-grained frequency resolution of 1.77 MHz, which allows the oscillator to tune into the Larmor frequencies of a group of qubits. Altogether, these circuits can be used in the development of a new quantum computing architecture which places the qubit arrays together with their accompanying electronics.
In this thesis, the readout of a silicon spin qubit by transmission at 200 GHz is investigated. The circuit presented, designed in a 22 nm FDSOI process, is intended to detect the quantum-state-dependant shift in resonant frequency of an LC tank. On-die mmWave frequency triplers are included to allow for characterization in a cryogenic probe station, with no external signals above 67 GHz. Using a variable capacitance as a room-temperature-compatible device-under-test, the ability to detect a change in impedance was verified. To the best of the author's knowledge, this is the highest-frequency circuit designed for RF readout of silicon qubits. Operating at 200 GHz reduces the size of certain passive components, such as hybrid couplers and resonator inductors, enabling further monolithic integration of quantum computers.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Solid-state quantum computers require classical electronics to control and readout individual qubits and to enable fast classical data processing [1-3]. Integrating both subsystems at deep cryogenic temperatures [4], where solid-state quantum processors operate best, may solve some major scaling challenges, such as system size and input/output (I/O) data management [5]. Spin qubits in silicon quantum dots (QDs) could be monolithically integrated with complementary metal-oxide-semiconductor (CMOS) electronics using very-large-scale integration (VLSI) and thus leveraging over wide manufacturing experience in the semiconductor industry [6]. However, experimental demonstrations of integration using industrial CMOS at mK temperatures are still in their infancy. Here we present a cryogenic integrated circuit (IC) fabricated using industrial CMOS technology that hosts three key ingredients of a silicon-based quantum processor: QD arrays (arranged here in a non-interacting 3x3 configuration), digital electronics to minimize control lines using row-column addressing and analog LC resonators for multiplexed readout, all operating at 50 mK. With the microwave resonators (6-8 GHz range), we show dispersive readout of the charge state of the QDs and perform combined time- and frequency-domain multiplexing, enabling scalable readout while reducing the overall chip footprint. This modular architecture probes the limits towards the realization of a large-scale silicon quantum computer integrating quantum and classical electronics using industrial CMOS technology.
Quantum computers hold a promise to solve intractable problems that can not be solved with classical computers. In quantum computers, information is processed in qubits as opposed to bits. The proper operation of qubits requires them to be operated in a quantum state; hence they need to be cooled down to temperatures well below l1K. Using qubits and their quantum mechanical property, quantum computers can achieve exponential speedup in solving certain computing problems compared to classical computers. However, this can only be achieved by employing thousands of qubits. At the current state of play, quantum computers are still far from practical. The current state-of-the-art solution dictates that each qubit needs multiple interconnects towards room temperature and requires bulky room temperature instruments for qubit readout and control. Clearly, this current solution will not scale well for a quantum computer with many qubits. In an effort to solve this issue, it has been proposed to realize dedicated integrated circuits for control and readout of the qubits and operate them closer to the qubits' operating temperature to enable scalability. The thesis presents the implementation of an integrated RF receiver for spin and superconducting qubit readout applications. The work aims to replace the bulky room temperature electronics with an integrated solution that operates at 4K to enable scalability and simplification of the quantum computing architecture. The receiver has been designed in the TSMC 40nm CMOS technology and has been characterized in room temperature and 4K. The measured performance shows that the receiver features a gain of 58 dB and a minimum double-sideband noise figure of 0.6 dB at 4K with an operating frequency of 6-8 GHz; a comparable performance to the current state-of-the-art room temperature electronics used for qubit readout. Moreover, this work demonstrates a qubit readout experiment with the integrated receiver in both room temperature and 4K. The qubit readout experiment shows a comparable qubit readout performance with the integrated receiver at room temperature. However, due to oscillation problems, a degradation in qubit readout performance with the chip operating at 4K is observed.