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International Conference on Information and Communication Technology Convergence (ICTC)

A Comparative Study of Quantum Circuit Mapping Techniques for NISQ Devices

You-Seok Lee, Jongheon Lee, Yousung Kang

Published Oct 14, 2025• 1 citation
Publisher

Abstract

Noisy Intermediate-Scale Quantum (NISQ) computers impose severe architectural constraints that prevent direct execution of logical quantum circuits. As a result, quantum circuit mapping—transforming ideal circuits into hardware-compatible forms—has become a critical task in quantum software toolchains. This paper presents a comparative study of key mapping techniques, focusing on circuit depth, SWAP gate overhead, and fidelity awareness. Through a case analysis on a 5-qubit Quantum Fourier Transform (QFT) circuit, we demonstrate the performance trade-offs of several prominent mapping strategies, including naive greedy routing, Qiskit’s SABRE, and CQC’s t|ket>. Our findings reveal that mapping technique selection has a profound impact on circuit quality and feasibility on real NISQ hardware.

DOI
10.1109/ictc66702.2025.11389032

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Noisy Intermediate-Scale Quantum (NISQ) computers impose severe architectural constraints that prevent direct execution of logical quantum circuits. As a result, quantum circuit mapping—transforming ideal circuits into hardware-compatible forms—has become a critical task in quantum software toolchains. This paper presents a comparative study of key mapping techniques, focusing on circuit depth, SWAP gate overhead, and fidelity awareness. Through a case analysis on a 5-qubit Quantum Fourier Transform (QFT) circuit, we demonstrate the performance trade-offs of several prominent mapping strategies, including naive greedy routing, Qiskit’s SABRE, and CQC’s t|ket>. Our findings reveal that mapping technique selection has a profound impact on circuit quality and feasibility on real NISQ hardware.
Quantum computers with a limited qubit connectivity require inserting SWAP gates for qubit routing, which increases gate execution errors and the impact of environmental noise due to an overhead in circuit depth. In this work, we benchmark various routing techniques considering random quantum circuits on one-dimensional and square lattice connectivities, employing both analytical and numerical methods. We introduce circuit fidelity as a comprehensive metric that captures the effects of SWAP and circuit depth overheads. Leveraging a novel approach based on the SABRE algorithm, we achieve up to 84%84\%84% higher average circuit fidelity for large devices within the NISQ range, compared to previously existing methods. Additionally, our results highlight that the optimal routing choice critically depends on the qubit count and the hardware characteristics, including gate fidelities and coherence times.
Quantum computing is gaining momentum in revolutionizing the way we approach complex problem-solving. However, the practical implementation of quantum algorithms remains a significant challenge due to the error-prone and hardware limits of near-term quantum devices. For instance, physical qubit connections are limited, which necessitates the use of quantum SWAP gates to dynamically transform the logical topology during execution. In addition, to optimize fidelity, it is essential to ensure that 1) the allocated hardware has a low error rate and 2) the number of SWAP gates injected into the circuit is minimized. To address these challenges, we propose a suite of algorithms: the Fidelity-aware Graph Extraction Algorithm (FGEA) is used to identify the hardware region with the lowest probability of error, the Frequency-based Mapping Algorithm (FMA) allocates logical-physical qubits that reduce the potential distance of topological transformation, and the Heuristic Routing Algorithm (HRA) searches for an optimal swapping injection strategy. We evaluate the proposed algorithms on the IBM-provided Noisy Intermediate-Scale Quantum (NISQ) computer, using a dataset consisting of 17 different quantum circuits of various sizes. The circuits are executed on the IBM Toronto Falcon processor. The three proposed algorithms outperform the existing SABRE algorithm in reducing the number of SWAP gates required. Therefore, our proposed algorithms hold significant promise in enhancing the fidelity and reducing the number of SWAP gates required in implementing Quantum algorithms.
Rapid advancement in the domain of quantum technologies have opened up researchers to the real possibility of experimenting with quantum circuits, and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise pose a challenge in smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit counts with recent emphasis on topology-aware (nearest-neighbour compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks, show that the fidelity of the circuit can be improved up to 3.37 × with an average improvement of 1.87 ×.
We present a routing-aware pruning strategy for quantum circuits that selectively removes parametric two-qubit gates whose computational contribution is outweighed by the fidelity cost of their execution, and assess it across both Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) architectures. Each two-qubit gate of a circuit is evaluated by comparing an architecture-independent lower bound on the fidelity cost of omitting the gate against a hardware-specific model for the routing execution cost in each setting. We additionally provide an analytical characterization of the pruning boundary as a function of rotation angle, qubit distance, and hardware noise. Simulations on benchmark circuits demonstrate gate count reductions of up to 48.6% and fidelity improvements of up to 47.7% in the NISQ regime, while a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates. These results establish routing-aware pruning as a practical and unified compilation strategy across the quantum computing stack.
Rapid advancement in the domain of quantum technologies has opened up researchers to the real possibility of experimenting with quantum circuits and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise poses a challenge in the smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit count with the recent emphasis on topology-aware (nearest-neighbor compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks show that the fidelity of the circuit can be improved up to 3.37X with an average improvement of 1.87X.
The development of complex circuits for practical applications in the current quantum computing ecosystem is based on basic primitives such as Bell states, which provide superposition, entanglement, and coherence. The range of domain-specific quantum applications has been greatly expanded by the availability of simulators and platforms such as IBM Quantum, which are supported by Qiskit. However, disparities between ideal simulator outputs and actual quantum processing unit (QPU) executions in the Noisy Intermediate-Scale Quantum (NISQ) era require the application of quantum error mitigation techniques. Limitations arise from hardware constraints in superconducting qubit systems and from the limited resources of classical simulators as quantum circuits grow. Quantum decoherence, which lowers gate fidelity and builds up at the circuit level with increasing depth, is specifically caused by material-induced flaws and interfaces. This creates a clear connection between circuit reliability, device performance, and material attributes. To address this, the current work uses both simulation and actual hardware on the IBM Sherbrooke 127-qubit processor to study three basic circuit classes over 4 to 10 qubits: the quantum Fourier transform, the Greenberger-Horne-Zeilinger state, and the W state. The study examines trade-offs between circuit complexity, noise robustness, and resource utilization by contrasting simulator and QPU results. The results imply that circuit fidelity can serve as an indirect probe of material-limited noise, opening the door to a framework for designing quantum circuits that accounts for both hardware and materials to achieve scalable quantum advantage.