Quantum computers are expected to surpass current modern computers in certain types of computations by utilizing quantum mechanical properties of atoms, molecules, and photons. Among the various systems being explored for realizing such computers, superconducting qubits have enabled many pioneering experimental demonstrations due to their ability to perform nonlinear operations and be integrated using semiconductor fabrication technologies. These quantum computers require operation at extremely low temperatures, around 10 mK, using dilution refrigerators. A major challenge at these temperatures is the heat inflow caused by wiring used to control and read out the qubits. This study reports on the development of a transmission line that can operate at low temperatures and achieves both low thermal inflow and low transmission loss in the 5 GHz band, which is used for qubit readout. Here we focus on the scalability of the transmission line and design a parallel set of transmission lines with low crosstalk.
Quantum computers are expected to surpass current modern computers in certain types of computations by utilizing quantum mechanical properties of atoms, molecules, and photons. Among the various systems being explored for realizing such computers, superconducting qubits have enabled many pioneering experimental demonstrations due to their ability to perform nonlinear operations and be integrated using semiconductor fabrication technologies. These quantum computers require operation at extremely low temperatures, around 10 mK, using dilution refrigerators. A major challenge at these temperatures is the heat inflow caused by wiring used to control and read out the qubits. This study reports on the development of a transmission line that can operate at low temperatures and achieves both low thermal inflow and low transmission loss in the 5 GHz band, which is used for qubit readout. Here we focus on the scalability of the transmission line and design a parallel set of transmission lines with low crosstalk.
Since superconducting quantum computers use microwave signals to control and readout their qubits, microwave transmission lines and circuits that can be used under cryogenic conditions are required. For microwave transmission lines, thermal insulation is essential to enhance wiring density and to prevent parasitic heating that can lead to increased computational errors. Thus, here we design and characterize a scalable, thermally insulated microwave transmission line. The transmission line designed for superconducting qubit readout at 5 GHz band achieves both thermal insulation and low loss, by employing resonator-based impedance matching in a microstripline structure. A flexible cable including eight planar transmission lines was designed, fabricated and characterized using S-parameter measurement, demonstrating low crosstalk below 40dB and signal attenuation of -23.5±0.07dB; this coincides with electromagnetic simulations. These microwave properties remained stable across a wide temperature range from room temperature down to 4 K, including steep gradients. The integration of chip attenuators further reduces thermal noise and protects sensitive cryogenic components. Our approach offers a promising solution for compact, high-density microwave wiring using flat cables under thermal gradients, necessary for large scale quantum computing.
Quantum computing promises an exponentially higher computational power than classical computers; although all the building blocks have become available, certain constraints still prevent quantum advantage. The fundamental challenge in building a practical quantum computer is integrating thousands of highly coherent qubits with the control and readout electronics. The need for a high‐coherence qubit drives the effort for quantum error correction algorithms to create fault‐tolerant quantum systems. Error correction becomes tangible in a quantum processor only in large numbers of qubits. Thus, the other challenge is reducing the number of physical interconnects (coaxial lines) between the quantum–classical interface and bulky room‐temperature electronics. To interface thousands of qubits, interconnects can be reduced by bringing the control and readout electronics near the quantum processor. Cryogenic complementary metal–oxide–semiconductor (CMOS) technology has been an ideal candidate for this purpose. Integrated control and readout at cryogenic temperatures require low power dissipation circuit designs and techniques such as frequency‐division multiplexing (FDM) due to the finite cooling power of a dilution refrigerator. Herein, an overview of each building block in a superconducting quantum computer is provided, focusing on scalability. Furthermore, this article is concluded with an outlook discussing current challenges and future directions for the scalable superconducting control and readout.
Scaling superconducting quantum processors to hundreds of qubits is essential for demonstrating quantum advantage and implementing quantum error correction codes with larger distances. A key challenge is integrating control and readout wiring without compromising cryogenic or electronic performance. To address this, we performed a systematic analysis of the thermal budget within a dilution refrigerator and developed high-density 0.5 mm SCuNi-CuNi coaxial cable sets optimized for heat load management. This enables the integration of 696 control lines and 40 readout amplification chains into a dilution refrigerator with a cooling power of 1 mW at 100 mK, maintaining a stable base temperature of ∼8 mK for over a year. We validated the platform's performance with two large-scale quantum processors: a 540-qubit processor with an average T1 of 35 μs and a 156-qubit processor with 182 tunable couplers, achieving average fidelities of 99.9% for single-qubit gates and 99.0% for two-qubit gates. This study demonstrates a viable high-density wiring solution for controlling and measuring processors at the 500-qubit scale and provides critical engineering insights for larger-scale quantum computing systems.
Today's hundred-qubit quantum computers require a dramatic scale up to millions of qubits to become practical for solving real-world problems. Although a variety of qubit technologies have been demonstrated, scalability remains a major hurdle. Superconducting (SC) qubits are one of the most mature and promising technologies to overcome this challenge. However, these qubits reside in a millikelvin cryogenic dilution fridge, isolating them from thermal and electrical noise. They are controlled by a rack-full of external electronics through extremely complex wiring and cables. Although thousands of qubits can be fabricated on a single chip and cooled down to millikelvin temperatures, scaling up the control and readout electronics remains an elusive goal. This is mainly due to the limited available cooling power in cryogenic systems constraining the wiring capacity and cabling heat load management. In this article, we focus on scaling up the number of XY-control lines by using cryogenic RF-photonic links. This is one of the major roadblocks to build a thousand qubit superconducting QC. We will first review and study the challenges of state-of-the-art proposed approaches, including cryogenic CMOS and deep-cryogenic photonic methods, to scale up the control interface for SC qubit systems. We will discuss their limitations due to the active power dissipation and passive heat leakage in detail. By analytically modeling the noise sources and thermal budget limits, we will show that our solution can achieve a scale up to a thousand of qubits. Our proposed method can be seamlessly implemented using advanced silicon photonic processes, and the number of required optical fibers can be further reduced by using wavelength division multiplexing (WDM).
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.