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Nature Electronics

A scalable superconducting nanowire memory array with row–column addressing

Owen Medeiros, Matteo Castellani, Valentin Karam, Reed A. Foster, Alejandro Simon, Francesca Incalza, Brenden Butters, Marco Colangelo, Karl K. Berggren

Published Jan 6, 2026• 5 citations
Publisher
DOI
10.1038/s41928-025-01512-0

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Superconducting Nanowire Integrated Circuits for Scalable Cryogenic Memory

Owen Medeiros

Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.

•May 1, 2025•0 citations
Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6 \,Mb/cm2^{2}2. The array operates at 1.3 1.3\,1.3K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a 4×44\times 44×4 array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of 10−510^{-5}10−5. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.
Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.