科学与技术探索

基于QUBO建模与量子退火的LDPC码混合译码研究

宇桐张

Published Jan 8, 2026• 0 citations

Abstract

Low-Density Parity-Check (LDPC) codes, as a class of high-efficiency error-correcting codes with sparse parity-check matrices, have demonstrated enormous potential in the field of communications since their rediscovery, and have become a core coding scheme especially in the fifth-generation (5G) wireless communication systems. To address the decoding problem of LDPC codes in complex channel environments, this paper proposes an innovative quantum-classical hybrid decoding architecture. By transforming the decoding problem into a Quadratic Unconstrained Binary Optimization (QUBO) problem, the architecture leverages the parallel processing capability of coherent optical quantum computers to accelerate the iterative decoding process. The research focuses on two typical scenarios specified in the 5G standard: the high-throughput scenario (dominated by BG1 with long code length and high code rate) and the low-complexity scenario (dominated by BG2 with short code length and low code rate). Through establishing a rigorous mathematical model, a hybrid decoder based on quantum annealing and the belief propagation algorithm is designed in this paper, and the Bayesian optimization method is adopted to adaptively adjust key parameters such as the maximum number of iterations and damping factor. This research provides an important theoretical foundation and practical scheme for the practical application of quantum computing in the field of communications.

DOI: 10.65196/fdddws55

Related papers

Maximum-Likelihood Channel Decoding with Quantum Annealing Machine

Naoki Ide, Tetsuya Asayama, Hiroshi Ueno +1 more

We formulate maximum likelihood (ML) channel decoding as a quadratic unconstraint binary optimization (QUBO) and simulate the decoding by the current commercial quantum annealing machine, D-Wave 2000Q. We prepared two implementations with Ising model formulations, generated from the generator matrix and the parity-check matrix respectively. We evaluated these implementations of ML decoding for low-density parity-check (LDPC) codes, analyzing the number of spins and connections and comparing the decoding performance with belief propagation (BP) decoding and brute-force ML decoding with classical computers. The results show that these implementations are superior to BP decoding in relatively short length codes, and while the performance in the long length codes deteriorates, the implementation from the parity-check matrix formulation still works up to 1k length with fewer spins and connections than that of the generator matrix formulation due to the sparseness of parity-check matrices of LDPC.

arXiv:2007.08689Jul 16, 202014 citations

Performance Analysis of Sub-Optimal LDPC Decoder for 5G using Belief Propagation Algorithm

Avinash Subramaniam M, Jay Sejpal, Pasupuleti Rithvij +2 more

Today's modern wireless communication systems demand extensive quality and computational power with an increase in day-to-day data-rate standards. The latest com-munication standards focus on low latency, high throughput, and reliable error correction capabilities which inspired us to explore the 5G New Generation (NR) technology. Low-Density Parity-Check Codes (LDPC) are known to have error correction capabilities that can achieve Shannon's maximum channel ca-pacity. Encoding of LDPC Codes features a sparse property that enables effortless decoding at the receiver end. Advancements in deep learning have helped in estimating the channel noise more accurately. The Iterative Belief Propagation-Convolutional Neural Network (BP-CNN) architecture involves a CNN block which is trained with a quadratic loss function concatenated to a standard BP Decoder. The proposed Iterative BP-CNN architecture with a Batch Normalization layer results in a better performance compared to the Iterative BP-CNN architecture as it standardizes the input to the CNN block and also solves the problem of vanishing gradients during backpropagation.

International Conference on Internet of Everything, Microwave Engineering, Communication and Networks (IEMECON)Dec 1, 20214 citations

An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA

Bilal Mejmaa, Malika Alami Marktani, Ismail Akharraz +1 more

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.

ComputersAug 14, 202411 citations

A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard

Anuj Verma, Rahul Shrestha

In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.

IEEE International Symposium on Circuits and Systems proceedingsSep 29, 202022 citations

On Quantum-Enhanced LDPC Decoding for Rayleigh Fading Channels

Utso Majumder, Aditya Das Sarma, Vishnu Vaidya +1 more

Quantum and Classical computers continue to work together in tight cooperation to solve difficult problems. The combination is thus suggested in recent times for decoding the Low Density Parity Check (LDPC) codes, for the next generation Wireless Communication systems. In this paper we have worked out the Quadratic Unconstrained Binary Optimization (QUBO) formulation for Rayleigh Fading channels for two different scenarios- channel state fully known and not known. The resultant QUBO are solved using D-Wave 2000Q Quantum Annealer and the outputs from the Annealer are classically postprocessed, invoking the notion of diversity. Simple minimum distance decoding of the available copies of the outputs led to improved performance, compared to picking the minimum-energy solution in terms of Bit Error Rate (BER). Apart from providing these results and the comparisons to fully classical Simulated Annealing (SA) and the traditional Belief Propagation (BP) based strategies, some remarks about diversity due to quantum processing are also spelt out.

arXiv:2209.11994IEEE/ACM Symposium on Edge Computing (SEC)Dec 1, 20221 citation

Low-Density Parity-Check Decoder Architectures for Integrated Circuits and Quantum Cryptography

Mario Milicevic

Forward error correction enables reliable one-way communication over noisy channels, by transmitting redundant data along with the message in order to detect and resolve errors at the receiver. Low-density parity-check (LDPC) codes achieve superior error-correction performance on Gaussian channels under belief propagation decoding, however, their complex parity-check matrix structure introduces hardware implementation challenges. This thesis explores how the quasi-cyclic structure of LDPC parity-check matrices can be exploited in the design of low-power hardware architectures for multi-Gigabit/second decoders realized in CMOS technology, as well as in the design and construction of multi-edge LDPC codes for long-distance (beyond 100km) quantum cryptography over optical fiber. A frame-interleaved architecture is presented with a path-unrolled message-passing schedule to reduce the complexity of routing interconnect in an integrated circuit decoder implementation. A proof-of-concept silicon test chip was fabricated in the 28nm CMOS technology node. The LDPC decoder chip supports the four codes presented in the IEEE 802.11ad standard, occupies an area of 3.41mm^2, and achieves an energy efficiency of 15pJ/bit while delivering a maximum throughput of 6.78Gb/s, and operating with a 202MHz clock at 0.9V supply. The test chip achieves the highest normalized energy efficiency among published CMOS-based decoders for the IEEE 802.11ad standard. A quasi-cyclic code construction technique is applied to a multi-edge LDPC code with block length of 10^6 bits in order to reduce the latency of LDPC decoding in the key reconciliation step of long-distance quantum key distribution. The GPU-based decoder achieves a maximum information throughput of 7.16Kb/s, and extends the current maximum transmission distance from 100km to 160km with a secret key rate of 4.10 x 10^(-7) bits/pulse under 8-dimensional reconciliation. The GPU-based decoder delivers up to 8.03x higher decoded information throughput over the upper bound on secret key rate for a lossy optical channel, thus demonstrating that key reconciliation with LDPC codes is no longer a post-processing bottleneck in quantum key distribution. The contributions presented in this thesis can be applied to future research in the implementation of silicon-based linear-program decoders for high-reliability channels, and single-chip solutions for quantum key distribution containing integrated photonics and post-processing algorithms.

Nov 1, 20173 citations