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IEEE Internet Computing

QTest: A Simulation Testbed for Distributed Quantum Computing and Networking With Deep Reinforcement Learning

Hao Chen, Baoxia Du, Ruidong Li

Published Dec 22, 2025• 1 citation
Publisher

Abstract

In Distributed Quantum Computing (DQC), quantum networks interconnect multiple Quantum Processing Units (QPUs) to overcome single-device limitations and enable cross-server computation. We present QTest, a modular simulation testbed for distributed quantum computing and networking. The platform employs Deep Reinforcement Learning (DRL)-based quantum circuit partitioning and distributed quantum network scheduling, coordinating cross-server operations under network constraints such as routing and channel utilization. With containerized QPU nodes and GPU-accelerated backends, QTest supports circuit execution across heterogeneous and geographically distributed environments. By enabling task partitioning, inter-node entanglement distribution, fidelity-aware routing, and latency-throughput evaluation, QTest provides a reproducible and extensible environment for protocol development and validation. Experimental results show that QTest achieves efficient runtime scalability under ideal conditions. Compared to CPU-based execution, GPU-accelerated distributed runs reduce execution time by up to an order of magnitude, validating the effectiveness of the proposed testbed.

DOI
10.1109/mic.2025.3646208

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In Distributed Quantum Computing (DQC), quantum networks interconnect multiple Quantum Processing Units (QPUs) to overcome single-device limitations and enable cross-server computation. We present QTest, a modular simulation testbed for distributed quantum computing and networking. The platform employs Deep Reinforcement Learning (DRL)-based quantum circuit partitioning and distributed quantum network scheduling, coordinating cross-server operations under network constraints such as routing and channel utilization. With containerized QPU nodes and GPU-accelerated backends, QTest supports circuit execution across heterogeneous and geographically distributed environments. By enabling task partitioning, inter-node entanglement distribution, fidelity-aware routing, and latency-throughput evaluation, QTest provides a reproducible and extensible environment for protocol development and validation. Experimental results show that QTest achieves efficient runtime scalability under ideal conditions. Compared to CPU-based execution, GPU-accelerated distributed runs reduce execution time by up to an order of magnitude, validating the effectiveness of the proposed testbed.
We describe the development of the NetQStack Simulator, a network-integrated simulation framework designed to evaluate distributed quantum computing (DQC) within data center environments. Our approach strictly models the network topology, classical control plane, and quantum data plane required to execute distributed quantum workloads. The simulator models classical and physical-layer protocol synchronization, schedules sub-circuit executions on individual Quantum Processing Units (QPUs), and routes entanglement generation requests across Bell State Measurement (BSM) nodes. With the ability to use external network-aware circuit partitioning software, and interface with an intelligent quantum network controller, this architecture enables researchers to execute fully distributed algorithms while rigorously evaluating the impact of network latency, routing heuristics, and control-plane overhead. Our early results demonstrate that a network-integrated approach provides useful insights when assessing the performance and scalability of distributed quantum algorithms.
Distributed quantum computing (DQC) is being actively investigated as a means of scaling the number of qubits across multiple connected quantum devices. This includes quantum circuit compilation and execution management on multiple quantum devices in the network. The latter aspect is very challenging because, while reducing the makespan of job batches remains a relevant objective, novel quantum-specific constraints must be considered, including QPU utilization, non-local gate rate, and the latency associated with queued DQC jobs. In this work, a range of scheduling strategies is proposed, simulated, and evaluated, including heuristics that prioritize resource maximization for QPU utilization, node selection based on heterogeneous network connectivity, asynchronous node release upon job completion, and a scheduling strategy based on reinforcement learning with proximal policy optimization. These approaches are benchmarked against traditional FIFO and LIST schedulers under varying DQC job types and network conditions for the allocation of DQC jobs to devices within a network.
Distributed Quantum Computing (DQC) enables scalable quantum execution by interconnecting multiple quantum processing units (QPUs) through quantum networks. In DQC, end-to-end performance is jointly affected by circuit partitioning, entanglement routing, scheduling, and heterogeneous hardware characteristics. However, existing studies often optimize these components independently, providing limited understanding of their cross-layer interactions. In this paper, we present a cross-layer joint-optimization study for DQC using the previously developed SimDisQ-Net simulator. Through simulations, we find that circuit orchestration is one of the dominant factors affecting distributed execution quality, while network-layer mechanisms provide secondary but still meaningful improvements. We further demonstrate that traditional communication metrics, such as hop count or remote-gate count alone, are insufficient predictors of execution quality due to the strong interaction among path fidelity, hardware characteristics, and circuit structure. Motivated by these findings, we propose a topology-aware fidelity proxy (TAFP) evaluation approach that approximates distributed execution fidelity, enabling efficient evaluation of candidate circuit optimizations without time-consuming simulation. Our results highlight the importance of integrated circuit-network orchestration for scalable DQC.
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Distributed quantum computing (DQC) connects multiple quantum processing units to overcome the scale limits of monolithic hardware. We introduce SeQUeNCe...DQC a new top-level module within the SeQUeNCe package that compiles monolithic circuits into topology-aware execution plans and coordinates their execution using SeQUeNCe's existing quantum-network modules and protocols. We validate SeQUeNCe...DQC by reproducing a two-node trapped-ion Grover experiment in simulation and comparing success probabilities with the reported 71% benchmark. We then evaluate how compiler strategy, topology, and memory capacity jointly govern distributed circuit execution time and success rate. In these experiments, our hybrid compilers successfully identified mixed TeleGate/TeleData execution plans that outperformed pure gate-teleportation strategies. By capturing the physical overhead of distributed quantum primitives, SeQUeNCe...DQC provides a rigorous platform for co-designing DQC software and hardware architectures.
Distributed Quantum Computing (DQC) addresses the physical scaling limitations of monolithic quantum processors by networking modular Quantum Processing Units (QPUs). Efficient execution of quantum algorithms on DQC architectures requires compiling them across QPUs while minimizing inter-QPU communication bottlenecks, primarily through circuit partitioning. However, current evaluations of state-of-the-art partitioning heuristics focus primarily on the total entanglement cost of the partitions, failing to capture the broader structural and temporal overheads introduced by distributed network constraints. This paper addresses this evaluation gap by applying established monolithic benchmarking metrics to partitioned distributed circuits to quantify the performance impact of network constraints. Using an open-source, automated evaluation pipeline, we systematically assess diverse partitioning algorithms across standardized workloads and quantum network topologies. Our empirical results reveal that partitioning algorithms with comparable entanglement costs can still introduce drastically different physical execution penalties. By exposing these hidden trade-offs, such as severe increases in circuit depth and substantial reductions in gate density, this study demonstrates that comprehensive circuit-level metrics are essential for guiding the future design of DQC compilers.