The abstract sets the scene, delivers the result, highlights the efficiency gain, and establishes the formal requirement for access to the mechanism. The greatest limitation to Fault-Tolerant Quantum Computing (FTQC) is the extreme resource overhead (C) required for logical gates, such as the T-Gate, with costs often exceeding \mathbf{100\text{x}}. This technical report presents a rigorous simulation, validated against real-world hardware noise data (IBM Torino calibration), which demonstrates the feasibility of a \mathbf{1000} logical qubit system. Model 13.7 proves that, even operating under the scenario of Extreme Cost Skepticism (\mathbf{C=150.0\text{x}}), the underlying architecture achieves a final Logical Fidelity of \mathbf{99.9707\%}. The strategic value lies in the efficiency: this architecture achieves the scale of 1000 coherent logical qubits with a minimal \mathbf{2.0\text{x}} physical overhead, fundamentally solving the hardware scaling problem that conventional methods face. This document serves as a Proof of Concept (Results and Validation). The specific mechanism of the DCC/Fractal Encoding that enables this low overhead is proprietary. Evaluation of the full architectural design and access to the validated code, which demonstrates how the 2.0\text{x} efficiency is achieved, requires the execution of a Non-Disclosure Agreement (NDA).
The abstract sets the scene, delivers the result, highlights the efficiency gain, and establishes the formal requirement for access to the mechanism. The greatest limitation to Fault-Tolerant Quantum Computing (FTQC) is the extreme resource overhead (C) required for logical gates, such as the T-Gate, with costs often exceeding \mathbf{100\text{x}}. This technical report presents a rigorous simulation, validated against real-world hardware noise data (IBM Torino calibration), which demonstrates the feasibility of a \mathbf{1000} logical qubit system. Model 13.7 proves that, even operating under the scenario of Extreme Cost Skepticism (\mathbf{C=150.0\text{x}}), the underlying architecture achieves a final Logical Fidelity of \mathbf{99.9707%}. The strategic value lies in the efficiency: this architecture achieves the scale of 1000 coherent logical qubits with a minimal \mathbf{2.0\text{x}} physical overhead, fundamentally solving the hardware scaling problem that conventional methods face. This document serves as a Proof of Concept (Results and Validation). The specific mechanism of the DCC/Fractal Encoding that enables this low overhead is proprietary. Evaluation of the full architectural design and access to the validated code, which demonstrates how the 2.0\text{x} efficiency is achieved, requires the execution of a Non-Disclosure Agreement (NDA).
Current fault-tolerant quantum computer (FTQC) architectures utilize several encoding techniques to enable reliable logical operations with restricted qubit connectivity. However, such logical operations demand additional memory overhead to ensure fault tolerance. Since the main obstacle to practical quantum computing is the limited qubit count, our primary mission is to design floorplans that can reduce memory overhead without compromising computational capability. Despite extensive efforts to explore FTQC architectures, even the current state-of-the-art floorplan strategy devotes 50% of memory space to this overhead, not to data storage, to guarantee unit-time random access to all logical qubits. In this paper, we propose an FTQC architecture based on a novel floorplan strategy, Load/Store Quantum Computer Architecture (LSQCA), which can achieve almost 100% memory density. The idea behind our architecture is to separate the whole memory regions into small computational space called Computational Registers (CR) and space-efficient memory space called Scan-Access Memory (SAM). We define an instruction set for these abstract structures and provide concrete designs named point-SAM and line-SAM architectures. With this design, we can improve the memory density by allowing variable-latency memory access while concealing the latency with other bottlenecks. We also propose optimization techniques to exploit properties of quantum programs observed in our static analysis, such as access locality in memory reference timestamps. Our numerical results indicate that LSQCA successfully leverages this idea. In a resource-restricted situation, a specific benchmark shows that we can achieve approximately 90% memory density with 5% increase in the execution time compared to a conventional floorplan, which achieves at most 50% memory density for unit-time random access. Our design is defined as an abstract form, making this principle ubiquitous and applicable to a wide range of quantum devices, qubit-connectivity configurations, and error-correcting codes.
Partially fault-tolerant quantum computing (FTQC) has recently emerged as a promising approach for the execution of megaquop-scale circuits with millions of logical operations. In this work, we demonstrate the strengths and the limitations of this approach by conducting quantum resource estimation (QRE) of the space--time-efficient analog rotation (STAR) architecture using realistic hardware specifications for superconducting processors, and compare it against the QRE of the full FTQC architecture. We show how the performance of the STAR architecture's protocols is affected by hardware improvements. We also reduce the space requirements for partial FTQC by developing a procedure leveraging code growth to decrease the size of a factory producing analog rotation states. Our results reveal a non-trivial dependence of the optimal pre-growth code distance on the rotation angle with respect to post-growth infidelity. Further, we analyze space--time trade-offs between the factory size and the error-mitigation overhead, and observe that in an application-agnostic setting, there is a Goldilocks zone for circuits in the regime of roughly 105--106 small-angle rotation gates. We show that quantum simulation of 2D Fermi--Hubbard model systems is a particularly well-suited application for the STAR architecture, requiring only hundreds of thousands of physical qubits and runtimes on the order of minutes for modest system sizes. Due to its favourable algorithmic scaling to larger system sizes, utility-scale simulation of the 2D Fermi--Hubbard model could potentially be attained using partial FTQC.
Quantum computing holds the promise of solving problems intractable for classical computers, but practical large-scale quantum computation requires error correction to protect against errors. Fault-tolerant quantum computing (FTQC) enables reliable execution of quantum algorithms, yet they often demand substantial physical qubit overhead. Resource-efficient FTQC architectures minimize the number of physical qubits required, saving more than half compared to other architectures, but impose constraints that introduce up to 4.7× higher runtime overhead. In this paper, we present TQC, a \underline{T}ableau-based \underline{Q}uantum \underline{C}ompiler framework that minimizes FTQC runtime overhead without requiring additional physical qubits. By leveraging operation reorderability and latency hiding through parallel execution, TQC reduces FTQC runtime overhead by \textbf{2.57×} on average. Furthermore, FTQC circuits often contain millions of gates, leading to substantial compilation overhead. To address this, we optimize the core data structure, the tableau, used in stabilizer formalism. We provide two tailored versions of the Tableau data type, each designed for different usage scenarios. These optimizations yield an overall performance improvement of more than \textbf{1000×} compared to state-of-the-art FTQC optimization tools.
We present the ENSEMBLE-001 pilot study, reconciling three independent analyses of the minimum energy required to operate a fault-tolerant quantum computer at the 1,000-logical-qubit scale. The physics energy floor is defined by Landauer's limit on irreversible operations, the thermodynamic cost of error syndrome extraction, and the minimum overhead for magic-state distillation of non-Clifford gates. Our reconciled analysis finds that this physics floor lies 10^16–10^18 below current practical energy projections. The three independent writer legs converge on this headline figure but diverge on three methodological points: the logical-operation convention, the wall-power midpoint assumption, and the direction of the efficiency parameter η. We find a wall-power midpoint of 10–100 kW for sustained operation. The spread in the energy floor is primarily attributable to the choice of logical-op convention rather than physical disagreement. We conclude by identifying open questions regarding the applicability of the Landauer bound to reversible syndrome extraction and the scaling of these uncertainties to the 10,000-logical-qubit scale. ## 1. Introduction Fault-tolerant quantum computing (FTQC) relies on quantum error correction to protect logical qubits from physical noise. As architectures scale toward 1,000 logical qubits, the energy required for sustained operation becomes a critical bottleneck. This preprint details the ENSEMBLE-001 pilot study, which reconciles three independent analyses (writer legs a, b, and c) of the energy floor for FTQC at this scale. We define the energy floor as the minimum thermodynamic and computational energy required, assuming idealized physical components. We compare this floor to current practical resource estimates and track the provenance of divergences across the three independent analyses. ## 2. Background FTQC encodes logical qubits into many physical qubits using stabilizer codes, most notably the surface code [1]. To perform uni
Obtaining a quantum advantage in practical applications over classical machines requires a fault-tolerant model of computation. However, the resource overhead of developing a fault-tolerant quantum computer (FTQC) architecture is quite high. Current state-of-the-art architecture designs promise constant-time access to logical qubits at the expense of a high qubit overhead, or qubit-dense layouts at the expense of increased latency in the execution of a quantum workload. In this paper, we propose (a) an architecture design that balances the tradeoff of execution time of workloads with the density of logical qubits by placing the surface code patches around the ancilla region, giving almost equal access of the ancilla region to all the data qubits, (b) design a novel algorithm to leverage the T-gate characteristics of the user workload to suggest the optimal placement strategy in the floorplan of our architecture, (c) a workload-selective fast-Y optimization knob that accelerates Y-basis measurements only for qubits whose Y-gate demand justifies the additional tile cost, and (d) explore the scope of executing multiple programs concurrently, which enhances the reconfigurability of our proposed design. Through numerical evaluation, we observe that the proposed architecture design maintains the cycles per instruction time close to optimal while using up to ∼21% fewer data tiles, and up to ∼90% efficiency under a 10-way concurrency.
Quantum computing offers promising potential for faster computation compared to classical computing, with the advantage of improved scaling as the problem size increases.Many fast quantum algorithms have been developed to solve specific problems using quantum computation, and they are expected to be applied to a wide range of fields, including quantum chemistry, condensed matter physics, and machine learning.However, the high cost of realizing physical systems to perform quantum computations makes resource-efficient implementation methods indispensable.In the first part of this thesis, we study the resource-efficient design of a fault-tolerant protocol based on quantum low-density parity-check (LDPC) codes.Scalable quantum computation to achieve the speed-ups over classical computation requires fault tolerance due to the vulnerability of quantum systems to noise.Fault-tolerant quantum computation (FTQC) expenses significant space and time overheads to achieve fault-tolerant quantum circuits from the original circuits intended to simulate.An FTQC protocol based on quantum LDPC codes has the attractive advantage of constant-space overhead, but has the disadvantage of requiring a long polynomial-time overhead.In this thesis, we present a polylogarithmic time overhead FTQC protocol based on quantum LDPC code, which is exponentially time efficient compared to conventional protocols while maintaining the advantage of the constant space overhead.This overhead is enjoyed even if the non-zero classical computation performing the decoding algorithms is considered.The second part of this thesis investigates the resource-efficient design of variational quantum algorithms (VQAs).The VQAs are a heuristic algorithm with promising applications in various fields.The VQAs can be performed by minimizing task-specific cost functions, typically defined as the expectation values of observables.However, it is known that the execution of variational quantum algorithms requires numerous quantum measurements, and their reduction is a significant challenge in algorithm implementation.In the first study of this part, we propose a new algorithm for calculating nonadiabatic couplings (NACs), which are important quantities in simulating molecular