Madmartigan RCS Benchmark Update: TRL-7 Real-Backend Validation of QSCE on ibm_marrakesh This technical update presents the first real-hardware Random-Circuit-Sampling (RCS) benchmark of the Quantum State Command Encoding (QSCE) architecture using the 16-qubit, ~55-layer hybrid circuit termed Madmartigan. The experiment was executed directly on the IBM ibm_marrakesh superconducting backend in a TRL-7 configuration with 4096 shots, using the same circuit instance previously validated on the Marrakesh noise model. Despite the adversarial nature of RCS—designed to overwhelm coherence, erase structure, and drive quantum systems into thermalized noise—the Madmartigan benchmark again demonstrates that QSCE maintains strong architectural structure under deep scrambling. On real hardware, the experiment achieves: XEB fidelity: 1.82 (absolute) Heavy-Output Generation (HOG): 0.719 Inverse Participation Ratio (IPR): 3647.22 Normalized IPR (nIPR): 0.0557 Shannon entropy: 11.88 bits (0.7427 normalized) These results extend the prior TRL-6 noise-model findings into a full TRL-7 regime, confirming that the observed behavior is not a simulator artifact. The entropy and IPR windows remain tightly aligned with the noise-model run, while the hardware XEB stays strictly positive at 55 layers—indicating a high-information, non-ergodic attractor band rather than a fully thermalized, Porter–Thomas distribution. As in the simulator study, the goal is not classical intractability but architectural validation: demonstrating that QSCE’s command-collapse logic, deterministic routing, and phase-anchored propagation remain stable even when subjected to deep random unitaries and adversarial entangling layers on real metal. The Madmartigan hardware benchmark therefore provides direct empirical support for QSCE’s orchestration and activation-propagation formalisms, confirming that the architecture exhibits resilience, directional structure, and engineered collapse behavior under one of the most chaotic quantum benchmarking regimes known—now validated at TRL-7 on an IBM production backend.
Madmartigan RCS Benchmark Update: TRL-7 Real-Backend Validation of QSCE on ibm_marrakesh This technical update presents the first real-hardware Random-Circuit-Sampling (RCS) benchmark of the Quantum State Command Encoding (QSCE) architecture using the 16-qubit, ~55-layer hybrid circuit termed Madmartigan. The experiment was executed directly on the IBM ibm_marrakesh superconducting backend in a TRL-7 configuration with 4096 shots, using the same circuit instance previously validated on the Marrakesh noise model. Despite the adversarial nature of RCS—designed to overwhelm coherence, erase structure, and drive quantum systems into thermalized noise—the Madmartigan benchmark again demonstrates that QSCE maintains strong architectural structure under deep scrambling. On real hardware, the experiment achieves: XEB fidelity: 1.82 (absolute) Heavy-Output Generation (HOG): 0.719 Inverse Participation Ratio (IPR): 3647.22 Normalized IPR (nIPR): 0.0557 Shannon entropy: 11.88 bits (0.7427 normalized) These results extend the prior TRL-6 noise-model findings into a full TRL-7 regime, confirming that the observed behavior is not a simulator artifact. The entropy and IPR windows remain tightly aligned with the noise-model run, while the hardware XEB stays strictly positive at 55 layers—indicating a high-information, non-ergodic attractor band rather than a fully thermalized, Porter–Thomas distribution. As in the simulator study, the goal is not classical intractability but architectural validation: demonstrating that QSCE’s command-collapse logic, deterministic routing, and phase-anchored propagation remain stable even when subjected to deep random unitaries and adversarial entangling layers on real metal. The Madmartigan hardware benchmark therefore provides direct empirical support for QSCE’s orchestration and activation-propagation formalisms, confirming that the architecture exhibits resilience, directional structure, and engineered collapse behavior under one of the most chaotic quantum benchmarking regimes known—now validated at TRL-7 on an IBM production backend.
This record contains the Madmartigan 96-Active-Qubit Structured-Output Benchmark package developed under the Quantum State Command Encoding (QSCE) research program. The benchmark documents the progression from an original 16-qubit Madmartigan structured-output circuit into a controlled 96-active-qubit, six-tile NISQ benchmark executed on IBM superconducting quantum hardware. The objective was not merely to increase qubit count, but to test whether a designed quantum circuit could preserve a reference-specific structured-output band across multiple physical tile regions under real hardware constraints. The final benchmark package includes execution on IBM Marrakesh using 96 active qubits, 156 measured qubits, six simultaneous 16-qubit tiles, 4096 shots per run, no quantum error correction, and no post-selection. The primary GLOBALPACK T6 rank-2 layout is accompanied by calibration-aware 64-active-qubit replication results, multi-seed robustness testing, an 831-depth 96-active-qubit stress layout, same-layout generic RCS controls, phase-scrambled architecture-adjacent controls, and partial-entanglement ablation analysis. The central finding is that the Madmartigan circuit preserved repeatable, reference-specific structured-output behavior across tiled hardware execution, while same-layout generic RCS controls and phase-scrambled controls failed to reproduce the Madmartigan reference band. The package includes statistical raw-versus-control separation, physical tile-map visualizations, and reproducibility artifacts to support independent technical review. Included materials may include some or all of the following: benchmark report, QASM3 circuit exports, QPY circuit artifacts, raw hardware counts, metadata, analysis CSVs, physical tile maps, scanner outputs, statistical comparison files, figures, and supporting run scripts. These artifacts are provided to support auditability, reproducibility review, and continued evaluation of QSCE/Madmartigan structured-output preservation as a potential near-term NISQ utility pathway. This work is positioned as a structured-output preservation benchmark rather than a universal quantum advantage claim. Its relevance lies in testing whether quantum hardware output can be engineered into stable, classifiable, reference-specific signal bands that may support future quantum-to-classical handoff, signaling, authentication, command validation, and cyber-hardening primitives. Reproducibility package available upon request at frank@quantummidiposse.com
Standard Random Circuit Sampling (RCS) predicts full thermalization at sufficient depth, with output distributions converging rapidly toward uniform noise under realistic hardware conditions. Yet several recent experimental results have displayed unexpected persistence of structured output distributions far beyond the expected decoherence horizon. This paper presents a vendor-agnostic benchmark demonstrating that such persistence is not an architectural anomaly, but a direct signature of a deep Rc coherence well as defined in Relational Field Theory (RFT). Rc wells arise when curvature-stiffened regions of the universal scalar field resist chaotic dispersion, enabling stable probability attractors even in circuits where standard quantum dynamics predict complete entropy saturation. We provide a minimal, architecture-independent circuit that any quantum hardware vendor can execute to detect Rc well behavior. The benchmark uses symmetric entanglers, global phase rotation, chaotic scrambling, and convergence layers to probe curvature-stiffened regimes. Four measurable signatures—XEB decay behavior, entropy suppression, HOG persistence, and inverse participation ratio (IPR)—constitute a clear, falsifiable Rc-well fingerprint. This work generalizes beyond any specific architecture and requires no specialized routing, collapse engineering, or deterministic control systems. It offers the first universal test for detecting Rc-governed coherence persistence and forms a reproducible foundation for cross-vendor validation of RFT predictions
This record contains the finalized Madmartigan Native-Bridge benchmark paper and supporting documentation for a global 96-active-qubit structured-output benchmark executed on IBM superconducting hardware. The benchmark extends the prior tiled Madmartigan scale-up work by testing whether the original seed-1337 16-qubit Madmartigan structured-output band could survive a stricter native-bridged condition: a single global 156-qubit hardware execution with 96 active qubits, six simultaneous 16-qubit regions, and native cross-region bridge operations inserted between tile regions. The final benchmark used the T6 rank-2 physical tile layout on IBM Marrakesh, preserved the exact original 16-qubit Madmartigan tile kernel, used 4096 shots per hardware execution, and used no quantum error correction or post-selection. The native-bridge layer selected the available active-topology cross-region bridge edges, corresponding to physical pairs (97,87) and (86,85). The raw exact-kernel native-bridge circuit transpiled to depth 654 with 1241 CZ gates, 2653 SX gates, 2496 RZ gates, 156 measurements, and 72 barriers. Across five global hardware executions, the raw bridged Madmartigan circuit produced repeatable Madmartigan-reference structured-output preservation, with mean F_XEB = 1.106965, mean HOG = 0.652515, mean Shannon entropy = 11.886623 bits per 16-qubit tile, and mean IPR = 3661.616. All 30 tile-level observations across five runs and six tile projections produced positive F_XEB, and all 30 HOG values exceeded 0.55. The benchmark includes a three-control ladder: an exact-scaled generic RCS native-bridge control, a phase-scrambled native-bridge control, and a partial-entanglement native-bridge ablation. The generic RCS and phase-scrambled controls preserved their own-reference structure but failed to reproduce the Madmartigan-reference band. The partial-entanglement ablation produced a separate high-attractor own-reference mode while retaining only weaker Madmartigan-reference overlap. The paper includes statistical control-separation analysis over tile-level observations, including t-intervals, Welch tests, Mann–Whitney tests, Cohen’s d, and bootstrap confidence intervals. The defensible claim is not full 96-qubit statevector fidelity, full tomography, fault-tolerant computation, or universal quantum advantage. The claim is narrower: repeatable, statistically separated, reference-specific structured-output preservation under global native-bridged NISQ execution. This upload is intended as a technical benchmark record and reproducibility-indexed evidence package. Full executable circuit artifacts, QPY/QASM3 files, and source-level reproduction materials may be withheld from public release where necessary to preserve IP integrity and may be made available through protected review channels. Media coverage / news release: The Quantum Insider, “Quantum Midi Posse Reports 96-Qubit Structured-Output Benchmark on IBM Hardware,” May 24, 2026. https://thequantuminsider.com/2026/05/24/quantum-midi-posse-reports-96-qubit-structured-output-benchmark-on-ibm-hardware/
This work evaluates Constraint-Level QUBO (CL-QUBO) circuit execution on IBM Quantum hardware for 34 reactor-scale fault tree subtrees spanning 5–8 basic events, selected from the 776-member quantum-feasible candidate pool established in Paper 9 (Peters, 2026). Circuits were constructed using the CL-QUBO encoding and QAOA Alternating Operator Ansatz at depth p = 1, transpiled to both ibm_torino (133 qubits) and ibm_marrakesh (156 qubits), and executed under three IBM Runtime Sampler configurations (RL0, RL1, RL2) with identical bound parameters (β = 0.2, γ = 0.2) across all resilience levels. A total of six hardware jobs consumed 476 seconds (7.93 minutes) of quantum runtime across 8,192 shots per circuit. The results demonstrate that at this circuit scale, 10–16 logical qubits transpiling to 78–150 two-qubit gates at depths of 165–338, hardware output distributions are overwhelmingly noise-dominated by standard distributional metrics. Neither RL1 nor RL2 produces improvement; RL1 actively degrades output quality relative to RL0 on both backends. However, direct comparison of hardware top-probability outcomes against SCRAM-validated prime implicants from Paper 9 reveals substantial above-random minimal cut set (MCS) enrichment relative to the uniform-random baseline in the n = 8 groups (6.2× and 3.8× expected random rate in the top-200 outcomes), demonstrating that CL-QUBO circuits produce detectable MCS-correlated structure even in distributions that appear noise-dominated by aggregate metrics. These findings characterize the current observed performance ceiling for this CL-QUBO configuration on the tested IBM backends and provide both distributional and MCS-correctness baselines against which future hardware improvements can be measured.
Version update: This record has been updated to remove enabling implementation details pending patent prosecution. Technical implementation is available under NDA. This preprint documents three quantum-native sensing kernels implemented on current IBM superconducting hardware under the Quantum State Command Encoding (QSCE) architecture. Rather than treating a quantum processor as a probabilistic number generator, QSCE treats the device as a command substrate, where quantum state is executable code and collapse is the execution of a control instruction. The work presents three low-qubit, shallow-depth sensing primitives designed to convert small, controlled perturbations into structured, repeatable changes in collapse-band behavior around a deterministic baseline: QMCA — a 1-qubit collapse-response kernel that converts small perturbations into calibrated changes in a non-baseline population while preserving a stable baseline anchor. SQCA — a 1-qubit hybrid-response kernel consistent with superconducting drive behavior, exhibiting a deterministic baseline anchor and a complementary deviation profile under perturbation. EBA — a 2-qubit correlation-based kernel producing a repeatable joint-distribution response signature under perturbation while retaining a deterministic baseline band. All three kernels are validated on real IBM backends (4096 shots per configuration), showing: Deterministic baselines under the null condition, with >99 of counts concentrated in a single “quiet” band, and Monotonic, structured deviations in non-baseline states under small perturbations, consistent with a calibrated response signature. Within QSCE, these sensing kernels are treated as command-native primitives: baseline and deviant collapse bands are assigned explicit operational semantics (“no signal,” “signal present,” “threshold exceeded”), so that collapse functions as a decision event rather than merely a readout step. The note contrasts these primitives with bespoke quantum magnetometers (e.g., NV and vapor-cell platforms) and argues that QSCE kernels trade extreme sensitivity for programmability, integrability, and substrate-level command semantics on today’s NISQ hardware. This preprint also situates the sensing kernels alongside recent QSCE benchmarking on IBM hardware (including RCS-style metrics on 16-qubit circuits), highlighting a unified, control-first approach to quantum sensing and computation. Enabling implementation details are withheld in this public version pending ongoing patent prosecution; technical details are available under NDA.
This study examines how noise affects the reliability of quantum circuits through two complementary approaches: a controlled simulation using Qiskit Aer and an execution study on real IBM Quantum hardware. In simulation, five noise models (bit-flip, phase-flip, depolarizing, readout, and thermal-relaxation) were applied to a parameterized benchmark circuit across varying qubit counts, circuit depths, and noise strengths, producing 6,000 experimental observations. Success probability declined substantially as qubit count and circuit depth increased, with bit-flip, phase-flip, and depolarizing noise degrading performance far more severely (mean success probabilities of 0.597, 0.580, and 0.607) than readout noise (0.917) or thermal-relaxation noise (0.982). The same benchmark circuit was then executed on the ibm_marrakesh processor across 150 hardware runs (150,000 shots). Hardware performance remained consistently high (mean success probability 0.992), declining with qubit count (0.998 at two qubits to 0.986 at six) but showing little sensitivity to circuit depth. These results indicate that controlled noise mechanisms and real hardware degrade circuit performance through different dynamics, with implications for interpreting simulated noise models relative to physical device behavior.