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Design of quasi-cyclic Tanner codes with low error floors

Gianluigi Liva, W.E. Ryan, Marco Chiani

Published Apr 3, 2006• 17 citations
OpenAlex

Abstract

Tanner codes represent a broad class of graph-based coding schemes, including low-density parity-check (LDPC) and turbo codes. Whereas many different classes of LDPC and turbo codes have been proposed and studied in the past decade, very little work has been performed on the broader class of Tanner codes. In this paper we propose a design technique which leads to efficiently encodable quasi-cyclic Tanner codes based on both Hamming and single parity check (SPC) nodes. These codes are characterized by fast message-passing decoders and can be encoded using shift-register-based circuits. The resulting schemes exhibit excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel. 1

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Low-Floor Tanner Codes via Hamming-Node or RSCC-Node Doping

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Design of Irregular Quasi-Cyclic LDPC Codes

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Abstract-In this paper, a novel methodology for design irregular quasi-cyclic LDPC codes is presented. The quasi-cyclic structure facilitates encoder and decoder implementation through shift-register-based circuits. The irregularity characteristic improves the code performance in waterfall region. The structure imposed on the bipartite graphs together with shifting matrix, Lead to a class of this code suitable for fast iterative decoding. The construction method results in a class of quasi-cyclic LDPC codes with girth of at least 6.The simulation results show, using the Sum Productive Decoder, this kinds of codes having excellent performance on the additive white Gaussian noise channels.

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We propose a technique to design finite-length irregular low-density parity-check (LDPC) codes over the binary-input additive white Gaussian noise (AWGN) channel with good performance in both the waterfall and the error floor region. The design process starts from a protograph which embodies a desirable degree distribution. This protograph is then lifted cyclically to a certain block length of interest. The lift is designed carefully to satisfy a certain approximate cycle extrinsic message degree (ACE) spectrum. The target ACE spectrum is one with extremal properties, implying a good error floor performance for the designed code. The proposed construction results in quasi-cyclic codes which are attractive in practice due to simple encoder and decoder implementation. Simulation results are provided to demonstrate the effectiveness of the proposed construction in comparison with similar existing constructions.

IEEE International Symposium on Information Theory (ISIT)•Jul 1, 2011•7 citations
Tanner codes represent a broad class of graph-based coding schemes, including low-density parity-check (LDPC) and turbo codes. Whereas many different classes of LDPC and turbo codes have been proposed and studied in the past decade, very little work has been performed on the broader class of Tanner codes. In this paper we propose a design technique which leads to efficiently encodable quasi-cyclic Tanner codes based on both Hamming and single parity check (SPC) nodes. These codes are characterized by fast message-passing decoders and can be encoded using shift-register-based circuits. The resulting schemes exhibit excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel. 1
In this paper, a novel methodology for designing structured generalized low-density parity-check (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call low-density parity-check (LDPC) code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.
In this paper, a novel methodology for designing structured generalized LDPC (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call LDPC code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.
We study the design of structured Tanner codes with low error-rate floors on the binary additive white Gaussian noise channel (BAWGNC) and the binary erasure channel (BEC). The design technique involves the “doping of standard LDPC protographs, meaning Hamming or recursive systematic convolutional (RSC) code constraints are used together with singleparity-check (SPC) constraints to construct a code’s protograph. We show that the doping of a “good graph with Hamming or RSC codes is a pragmatic approach that frequently results in a code with a good threshold and very low error-rate floor. We focus on low-rate Tanner codes, in part because the design of low-rate, low-floor LDPC codes is particularly difficult.
We study the design of structured Tanner codes with low error-rate floors on the AWGN channel. The design technique involves the “doping” of standard LDPC (proto-)graphs, by which we mean Hamming or recursive systematic convolutional (RSC) code constraints are used together with single-parity-check (SPC) constraints to construct a code’s protograph. We show that the doping of a “good” graph with Hamming or RSC codes is a pragmatic approach that frequently results in a code with a good threshold and very low error-rate floor. We focus on low-rate Tanner codes, in part because the design of low-rate, low-floor LDPC codes is particularly difficult. Lastly, we perform a simple complexity analysis of our Tanner codes and examine the performance of lower-complexity, suboptimal Hamming-node decoders.
Abstract-In this paper, a novel methodology for design irregular quasi-cyclic LDPC codes is presented. The quasi-cyclic structure facilitates encoder and decoder implementation through shift-register-based circuits. The irregularity characteristic improves the code performance in waterfall region. The structure imposed on the bipartite graphs together with shifting matrix, Lead to a class of this code suitable for fast iterative decoding. The construction method results in a class of quasi-cyclic LDPC codes with girth of at least 6.The simulation results show, using the Sum Productive Decoder, this kinds of codes having excellent performance on the additive white Gaussian noise channels.
We propose a technique to design finite-length irregular low-density parity-check (LDPC) codes over the binary-input additive white Gaussian noise (AWGN) channel with good performance in both the waterfall and the error floor region. The design process starts from a protograph which embodies a desirable degree distribution. This protograph is then lifted cyclically to a certain block length of interest. The lift is designed carefully to satisfy a certain approximate cycle extrinsic message degree (ACE) spectrum. The target ACE spectrum is one with extremal properties, implying a good error floor performance for the designed code. The proposed construction results in quasi-cyclic codes which are attractive in practice due to simple encoder and decoder implementation. Simulation results are provided to demonstrate the effectiveness of the proposed construction in comparison with similar existing constructions.