Abstract The immense resource overhead of full quantum error correction (QEC) presents a formidable barrier to achieving fault-tolerant quantum computation. This paper introduces a hybrid analog-digital quantum processor architecture designed as a pragmatic strategy for achieving "mid-scale fault tolerance" (MSFT). We formally define MSFT as a hardware-level error suppression scheme that achieves a fidelity gain by replacing deep, error-prone digital gate sequences with single, high-fidelity analog evolution blocks. The architecture comprises a programmable digital core for state preparation and measurement, coupled to an analog co-processor that executes computationally intensive Hamiltonian evolutions. This approach reduces the effective logical depth and error accumulation for algorithms like VQE. We validate this claim with statistically robust simulations on standard molecular Hamiltonians (LiH and BeH₂), demonstrating a significant performance advantage over purely digital systems based on an aggregation of 50 independent simulation trials. The analysis includes scalability and a discussion of the critical digital-analog interface, proposing trapped-ion and neutral-atom systems as viable physical platforms.
Abstract The immense resource overhead of full quantum error correction (QEC) presents a formidable barrier to achieving fault-tolerant quantum computation. This paper introduces a hybrid analog-digital quantum processor architecture designed as a pragmatic strategy for achieving "mid-scale fault tolerance" (MSFT). We formally define MSFT as a hardware-level error suppression scheme that achieves a fidelity gain by replacing deep, error-prone digital gate sequences with single, high-fidelity analog evolution blocks. The architecture comprises a programmable digital core for state preparation and measurement, coupled to an analog co-processor that executes computationally intensive Hamiltonian evolutions. This approach reduces the effective logical depth and error accumulation for algorithms like VQE. We validate this claim with statistically robust simulations on standard molecular Hamiltonians (LiH and BeH₂), demonstrating a significant performance advantage over purely digital systems based on an aggregation of 50 independent simulation trials. The analysis includes scalability and a discussion of the critical digital-analog interface, proposing trapped-ion and neutral-atom systems as viable physical platforms.
Abstract The immense resource overhead of full quantum error correction (QEC) presents a formidable barrier to achiev- ing fault-tolerant quantum computation. This paper introduces a hybrid analog-digital quantum processor architecture designed as a pragmatic strategy for achieving ”mid-scale fault tolerance” (MSFT). We formally define MSFT as a hardware-level error suppression scheme that achieves a fidelity gain by replacing deep, error-prone digital gate sequences with single, high-fidelity analog evolution blocks. The architecture comprises a programmable digital core for state preparation and measurement, coupled to an analog co-processor that executes computationally intensive Hamiltonian evolutions. This approach reduces the effective logical depth and error accumulation for algorithms like VQE. We validate this claim with statistically robust simulations on standard molecular Hamiltonians (LiH and BeH), demonstrating a significant performance advantage over purely digital systems based on an aggregation of 50 independent simulation trials. The analysis includes scalability and a discussion of the critical digital-analog interface, proposing trapped-ion and neutral-atom systems as viable physical platforms
The transition from noisy intermediate-scale quantum (NISQ) processors to large-scale fault-tolerant machines requires more than incremental improvements in physical qubit fidelity. While advances in quantum error correction (QEC) theory continue to lower the theoretical overhead of quantum computing, much of this research remains abstracted from the physical realities of qubit implementations. This disconnect often results in hardware-agnostic designs that are inefficient or impractical to build. In this dissertation, I identify three primary gaps between theoretical QEC research and practical hardware: (1) the high levels of noise and temporal instability in experimental devices that impede scalable QEC; (2) the prohibitively large qubit and time costs of useful algorithms, driven largely by the limitations of the standard surface code; and (3) the failure of current resource estimates to account for hardware-level constraints, such as limited connectivity and the complexity of implementing non-local operations. To bridge these gaps, I propose a holistic, cross-stack approach where the error correction protocols and the physical hardware are designed in concert. By developing realistic device models and hardware-aware solutions at the lowest levels of the software stack, we can accelerate the path toward functional fault-tolerance. I present my work across three research thrusts: first, leveraging codesign to mitigate hardware-specific noise and reduce physical error rates; second, developing software tools for fault-tolerant quantum computers to reduce the space-time overhead of the QEC layer; and third, proposing two novel hardware-aware QEC architectures that provide practical, high-performance routes to scalable quantum computation.
Quantum computation faces significant challenges due to the inherent fragility of quantum states and the susceptibility of qubits to environmental noise. Achieving fault-tolerant quantum computation necessitates robust error correction strategies. This paper proposes a novel self-correcting hardware-software co-design approach specifically tailored for quantum processors. The core claim is that integrating self-correction mechanisms within both the hardware and software layers is paramount for realizing fault-tolerant quantum computation. This approach utilizes redundant hardware architectures alongside sophisticated error detection and correction codes, complemented by a dynamic software layer that intelligently responds to hardware errors. The proposed system aims to minimize the impact of errors by proactively adapting to the detected faults. This represents a fundamentally new holistic approach to fault tolerance, shifting the paradigm from solely relying on post-processing error correction to embedding correction capabilities directly into the quantum processor's architecture and control system. The key performance indicators (KPIs) for this system include reduced qubit error rates, increased computation fidelity, and improved overall quantum processor reliability. This work lays the groundwork for future advancements in quantum computing by addressing a critical bottleneck in the path towards practical, fault-tolerant quantum computation.
Quantum processors have the potential to significantly advance our understanding of quantum systems. In particular, the programmability of digital quantum devices enables access to highly tunable quantum dynamics and observables. The central challenge, however, is suppressing errors, making quantum error correction essential for large-scale algorithms. In this thesis, I present work on quantum processing with reconfigurable atom arrays, with experiments featuring up to 448 neutral atom qubits, high two-qubit gate fidelities, arbitrary connectivity, and mid-circuit qubit readout and reuse. Using this system, I describe how we realize gate-based quantum simulations. In particular, we experimentally study Kitaev’s honeycomb model and explore hardware-efficient fermion-to-qubit encodings. We then leverage unique opportunities with atoms to study the key building blocks of scalable quantum error correction. These include below-threshold performance, deep computation at constant entropy, and universal logical gates. Together, these experiments highlight unique near-term opportunities with atom arrays and chart a path toward future large-scale atomic processors.
Abstract We introduce a hardware-specific, problem-dependent digital-analog quantum algorithm of a counterdiabatic quantum dynamics tailored for optimization problems. Specifically, we focus on trapped-ion architectures, taking advantage from global Mølmer–Sørensen gates as the analog interactions complemented by digital gates, both of which are available in the state-of-the-art technologies. We show an optimal configuration of analog blocks and digital steps leading to a substantial reduction in circuit depth compared to the purely digital approach. This implies that, using the proposed encoding, we can address larger optimization problem instances, requiring more qubits, while preserving the coherence time of current devices. Furthermore, we study the minimum gate fidelity required by the analog blocks to outperform the purely digital simulation, finding that it is below the best fidelity reported in the literature. To validate the performance of the digital-analog encoding, we tackle the maximum independent set problem, showing that it requires fewer resources compared to the digital case. This hybrid co-design approach paves the way towards quantum advantage for efficient solutions of quantum optimization problems.
Quantum computing is positioned to be a transformative technology to key areas of scientific interest such as quantum chemistry, material science, and cryptography. At a hardware level, recent years have seen broad progress in a variety of qubit modalities, however, error rates are still orders of magnitude higher than what is necessary for large-scale quantum programs. This gap in error rates motivates the use of quantum error correction (QEC) and the realization of fault-tolerant quantum computing (FTQC), yet today, although the theory of FTQC is promising, effectively connecting it to real devices poses significant challenges. In this dissertation we study opportunities for more efficient and scalable FTQC architectures through the co-design of quantum hardware and software. We first look at how unique hardware capabilities in quantum computers made from 2D arrays of optically trapped atoms can improve QEC performance. For computation, we study how longer-range interactions between atoms can enable a novel embedding of QEC blocks on physical qubits that improves logical-level connectivity. For memory, we study how mid-circuit movement of atoms can effectively implement higher encoding rate QEC codes, creating a qubit-efficient memory system. We next consider the performance impact of real-time classical systems in FTQC architectures, and explore the use of speculation to improve large-scale decoding systems. Finally, we study how software systems can be used to improve QEC designs. We consider the problem of QEC circuit optimization, and study an automated approach based on iterative optimization of performance-reducing subcircuits.