Abstract The trapped-ion architecture was the first platform to demonstrate quantum gate operations in 1995 and continues to be a leading candidate for building a fault-tolerant quantum computer. This chapter provides a brief background on common performance metrics and nomenclature, summarizes the state of the art, and places them in context within the larger pursuit of error-corrected quantum computers. Current research thrusts in academia and industry are referenced, and an example roadmap is examined to show where the platform is right now and where it might be headed on the road to realizing a scaled-up device.
Abstract The trapped-ion architecture was the first platform to demonstrate quantum gate operations in 1995 and continues to be a leading candidate for building a fault-tolerant quantum computer. This chapter provides a brief background on common performance metrics and nomenclature, summarizes the state of the art, and places them in context within the larger pursuit of error-corrected quantum computers. Current research thrusts in academia and industry are referenced, and an example roadmap is examined to show where the platform is right now and where it might be headed on the road to realizing a scaled-up device.
This is the second paper in a series of papers providing an overview of different quantum computing hardware platforms from an industrial end-user perspective. It follows our first paper on neutral-atom quantum computing. In the present paper, we provide a survey on the current state-of-the-art in trapped-ion quantum computing, taking up again the perspective of an industrial end-user. To this end, our paper covers, on the one hand, a comprehensive introduction to the physical foundations and mechanisms that play an important role in operating a trapped-ion quantum computer. On the other hand, we provide an overview of the key performance metrics that best describe and characterise such a device's current computing capability. These metrics encompass performance indicators such as qubit numbers, gate times and errors, native gate sets, qubit stability and scalability as well as considerations regarding the general qubit types and trap architectures. In order to ensure that these metrics reflect the current state of trapped-ion quantum computing as accurate as possible, they have been obtained by both an extensive review of recent literature and, more importantly, from discussions with various quantum hardware vendors in the field. We combine these factors and provide - again from an industrial end-user perspective - an overview of what is currently possible with trapped-ion quantum computers, which algorithms and problems are especially suitable for this platform, what are the relevant end-to-end wall clock times for calculations, and what might be possible with future fault-tolerant trapped-ion quantum computers.
<!--HTML-->Trapped ions are one of the leading and furthest developed technologies in quantum computing. However, despite higher quality operations than on any other platform and the absence of variations in qubit quality, the road to fault-tolerant quantum computing remains long and steep. In this talk, I will briefly review the state of the art of the trapped-ion platform, illustrate the current attempts to scaling up to larger numbers of qubits and highlight the challenges faced in control electronics and reliable manufacturing.
We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes.
We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations.
Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.
Abstract The future of quantum information processing requires a stable hardware platform to execute quantum circuits reliably and with low error rates, such that solutions for industrial applications can be built on top of it. Trapped-ion quantum computing, among other platforms, currently proves to be very suitable for the transition from tabletop, lab-based experiments to rack-mounted, on-premise systems which allow operation in data center environments. Several technical challenges need to be solved and controlling many degrees of freedom needs to be optimized and automated, before industrial applications can be successfully implemented on quantum computers situated within data centers. These necessary developments range from the architecture of an ion trap that fundamentally defines the supported instruction sets, over the control electronics and laser systems, which limit the quality of qubit operations, to the optimized compilation of quantum circuits based on qubit properties and gate fidelities. In this chapter, we give an introduction to the ion-trap quantum computing platform, present the current technical state of the art of Alpine Quantum Technologies’ ion-trapping hardware and rack-based quantum computing systems, and highlight parts of the execution stack.
Ion trap is one of the leading physical platforms to implement quantum computation. Currently, high-fidelity elementary quantum operations above the fault-tolerant threshold, including state preparation, measurement and universal gates, have been demonstrated for tens of ionic qubits. One important future research direction is to further enlarge the qubit number to the scale required for solving practical problems while maintaining the high performance of individual qubits. This paper introduces the current mainstream schemes for scalable ion trap quantum computation like quantum charge-coupled device (QCCD) and ion-photon quantum network, and describes the main limiting factors in current research. Then we further explore new schemes to scale up the qubit number like two-dimensional ion crystals and dual-type qubit, and discuss the future research directions.
The pursuit of a universal, fault-tolerant quantum computer has transformed quantum computing from a predominantly theoretical discipline into a rapidly diversifying hardware ecosystem. This review presents a comprehensive and technically grounded analysis of the principal physical qubit modalities: superconducting circuits, trapped ions, photonic platforms, neutral atoms, semiconductor spin qubits, and topological approaches, focusing on their underlying operating principles, performance characteristics, and system-level constraints. We examine how these qubit technologies are embedded within scalable quantum processor architectures, including control and readout infrastructures, connectivity topologies, and quantum error correction strategies. The review provides a comparative study of key performance metrics, such as coherence times, gate fidelities, error rates, and scalability, reveals fundamental trade-offs between speed, robustness, and operational complexity that shape distinct technological roadmaps and target applications. We further highlight the ongoing transition from noisy intermediate-scale quantum (NISQ) devices toward architectures centred on logical qubits, driven by advances in materials engineering, precision control, and quantum information theory. Together, these developments sketch the emerging routes toward fault-tolerant quantum computing and practical quantum advantage, while offering readers a coherent entry point and reference guide to the current quantum hardware landscape.