Ion-Based Quantum Computing Hardware: Performance and End-User Perspective
Thomas Strohm, Karen Wintersperger, Florian Dommert, Daniel Basilewitsch, Reuber, Georg, Andrey Hoursanov, Thomas Ehmer, Davide Vodola, Sebastian Markus Luber
This is the second paper in a series of papers providing an overview of different quantum computing hardware platforms from an industrial end-user perspective. It follows our first paper on neutral-atom quantum computing. In the present paper, we provide a survey on the current state-of-the-art in trapped-ion quantum computing, taking up again the perspective of an industrial end-user. To this end, our paper covers, on the one hand, a comprehensive introduction to the physical foundations and mechanisms that play an important role in operating a trapped-ion quantum computer. On the other hand, we provide an overview of the key performance metrics that best describe and characterise such a device's current computing capability. These metrics encompass performance indicators such as qubit numbers, gate times and errors, native gate sets, qubit stability and scalability as well as considerations regarding the general qubit types and trap architectures. In order to ensure that these metrics reflect the current state of trapped-ion quantum computing as accurate as possible, they have been obtained by both an extensive review of recent literature and, more importantly, from discussions with various quantum hardware vendors in the field. We combine these factors and provide - again from an industrial end-user perspective - an overview of what is currently possible with trapped-ion quantum computers, which algorithms and problems are especially suitable for this platform, what are the relevant end-to-end wall clock times for calculations, and what might be possible with future fault-tolerant trapped-ion quantum computers.
This is the second paper in a series of papers providing an overview of different quantum computing hardware platforms from an industrial end-user perspective. It follows our first paper on neutral-atom quantum computing. In the present paper, we provide a survey on the current state-of-the-art in trapped-ion quantum computing, taking up again the perspective of an industrial end-user. To this end, our paper covers, on the one hand, a comprehensive introduction to the physical foundations and mechanisms that play an important role in operating a trapped-ion quantum computer. On the other hand, we provide an overview of the key performance metrics that best describe and characterise such a device's current computing capability. These metrics encompass performance indicators such as qubit numbers, gate times and errors, native gate sets, qubit stability and scalability as well as considerations regarding the general qubit types and trap architectures. In order to ensure that these metrics reflect the current state of trapped-ion quantum computing as accurate as possible, they have been obtained by both an extensive review of recent literature and, more importantly, from discussions with various quantum hardware vendors in the field. We combine these factors and provide - again from an industrial end-user perspective - an overview of what is currently possible with trapped-ion quantum computers, which algorithms and problems are especially suitable for this platform, what are the relevant end-to-end wall clock times for calculations, and what might be possible with future fault-tolerant trapped-ion quantum computers.
Abstract We present an industrial end-user perspective on the current state of quantum computing hardware for one specific technological approach, the neutral atom platform. Our aim is to assist developers in understanding the impact of the specific properties of these devices on the effectiveness of algorithm execution. Based on discussions with different vendors and recent literature, we discuss the performance data of the neutral atom platform. Specifically, we focus on the physical qubit architecture, which affects state preparation, qubit-to-qubit connectivity, gate fidelities, native gate instruction set, and individual qubit stability. These factors determine both the quantum-part execution time and the end-to-end wall clock time relevant for end-users, but also the ability to perform fault-tolerant quantum computation in the future. We end with an overview of which applications have been shown to be well suited for the peculiar properties of neutral atom-based quantum computers.
The pursuit of a universal, fault-tolerant quantum computer has transformed quantum computing from a predominantly theoretical discipline into a rapidly diversifying hardware ecosystem. This review presents a comprehensive and technically grounded analysis of the principal physical qubit modalities: superconducting circuits, trapped ions, photonic platforms, neutral atoms, semiconductor spin qubits, and topological approaches, focusing on their underlying operating principles, performance characteristics, and system-level constraints. We examine how these qubit technologies are embedded within scalable quantum processor architectures, including control and readout infrastructures, connectivity topologies, and quantum error correction strategies. The review provides a comparative study of key performance metrics, such as coherence times, gate fidelities, error rates, and scalability, reveals fundamental trade-offs between speed, robustness, and operational complexity that shape distinct technological roadmaps and target applications. We further highlight the ongoing transition from noisy intermediate-scale quantum (NISQ) devices toward architectures centred on logical qubits, driven by advances in materials engineering, precision control, and quantum information theory. Together, these developments sketch the emerging routes toward fault-tolerant quantum computing and practical quantum advantage, while offering readers a coherent entry point and reference guide to the current quantum hardware landscape.
Abstract The future of quantum information processing requires a stable hardware platform to execute quantum circuits reliably and with low error rates, such that solutions for industrial applications can be built on top of it. Trapped-ion quantum computing, among other platforms, currently proves to be very suitable for the transition from tabletop, lab-based experiments to rack-mounted, on-premise systems which allow operation in data center environments. Several technical challenges need to be solved and controlling many degrees of freedom needs to be optimized and automated, before industrial applications can be successfully implemented on quantum computers situated within data centers. These necessary developments range from the architecture of an ion trap that fundamentally defines the supported instruction sets, over the control electronics and laser systems, which limit the quality of qubit operations, to the optimized compilation of quantum circuits based on qubit properties and gate fidelities. In this chapter, we give an introduction to the ion-trap quantum computing platform, present the current technical state of the art of Alpine Quantum Technologies’ ion-trapping hardware and rack-based quantum computing systems, and highlight parts of the execution stack.
Ion trap is one of the leading physical platforms to implement quantum computation. Currently, high-fidelity elementary quantum operations above the fault-tolerant threshold, including state preparation, measurement and universal gates, have been demonstrated for tens of ionic qubits. One important future research direction is to further enlarge the qubit number to the scale required for solving practical problems while maintaining the high performance of individual qubits. This paper introduces the current mainstream schemes for scalable ion trap quantum computation like quantum charge-coupled device (QCCD) and ion-photon quantum network, and describes the main limiting factors in current research. Then we further explore new schemes to scale up the qubit number like two-dimensional ion crystals and dual-type qubit, and discuss the future research directions.
Neutral atom quantum computing utilizes laser-trapped neutral atoms as qubits and realizes quantum logic gate operations through Rydberg-state interactions. In recent years, it has become one of the most vibrant directions in quantum computing hardware. This paper systematically reviews the working principles of neutral-atom quantum computers, including qubit encoding, atom trapping and manipulation, Rydberg states and interactions, the Rydberg blockade quantum gate mechanism, and atom rearrangement with reconfigurable architectures. The mainstream technical routes are surveyed, represented by optical tweezer arrays combined with Rydberg interactions, optical lattice schemes, and dipole trap arrays. A panoramic review is provided of domestic and international research progress from theoretical foundations in 2000 to the latest achievements in 2026, including thousand-qubit-scale systems, logical qubits, and quantum error correction experiments. Key breakthroughs are highlighted, such as the 6100-atom qubit array, continuous operation of a 3000-qubit system, quantum simulation of the Kitaev honeycomb model, toric code error correction demonstrations, encoding rates exceeding 1/2, and fault-tolerant architectures. The core bottlenecks are analyzed in depth, including the scalability--fidelity trade-off, engineering implementation of quantum error correction, atom loss and mid-circuit replenishment, laser system industrialization, control electronics scalability, and long-distance quantum interconnection. This paper aims to provide a systematic reference for academic research and technological development in this field.
Quantum computing promises to revolutionize several scientific and industrial domains by tackling problems that are intractable for classical supercomputers. At the centre of this effort is the quantum processor unit (QPU), implemented today across multiple physical qubit platforms. This review provides a comparative analysis of the state of quantum processors as of late 2024/early 2025, focusing on superconducting qubits, trapped ions, photonic systems, neutral atoms, silicon spin qubits, and emerging topological approaches. We compile and compare recent processor generations such as IBM’s Heron family, Google’s updated Sycamore-class devices, Quantinuum’s H-series, IonQ’s Aria and Forte, neutral-atom platforms with more than 1,000 trapped atoms, and silicon spin prototypes like Tunnel Falls. Key performance metrics, including qubit count, gate and readout fidelity, coherence time, operation speed, and holistic benchmarks such as Quantum Volume (QV) and Algorithmic Qubits (#AQ) are examined with reference to concrete experimental milestones. We discuss algorithmic capabilities demonstrated on current hardware, early realizations of logical qubits and fault-tolerant primitives, and the distinction between feasibility-oriented “quantum advantage” experiments and emerging signs of practical “quantum utility”. Finally, we outline the main technical bottlenecks for each platform on the path from today’s NISQ devices toward universal fault-tolerant quantum computers.