Neutral atom quantum computing hardware: performance and end-user perspective
Karen Wintersperger, Florian Dommert, Thomas Ehmer, Andrey Hoursanov, Johannes Klepsch, Wolfgang Mauerer, Georg Reuber, Thomas Strohm, Ming Yin, Sebastian Markus Luber
Abstract We present an industrial end-user perspective on the current state of quantum computing hardware for one specific technological approach, the neutral atom platform. Our aim is to assist developers in understanding the impact of the specific properties of these devices on the effectiveness of algorithm execution. Based on discussions with different vendors and recent literature, we discuss the performance data of the neutral atom platform. Specifically, we focus on the physical qubit architecture, which affects state preparation, qubit-to-qubit connectivity, gate fidelities, native gate instruction set, and individual qubit stability. These factors determine both the quantum-part execution time and the end-to-end wall clock time relevant for end-users, but also the ability to perform fault-tolerant quantum computation in the future. We end with an overview of which applications have been shown to be well suited for the peculiar properties of neutral atom-based quantum computers.
Abstract We present an industrial end-user perspective on the current state of quantum computing hardware for one specific technological approach, the neutral atom platform. Our aim is to assist developers in understanding the impact of the specific properties of these devices on the effectiveness of algorithm execution. Based on discussions with different vendors and recent literature, we discuss the performance data of the neutral atom platform. Specifically, we focus on the physical qubit architecture, which affects state preparation, qubit-to-qubit connectivity, gate fidelities, native gate instruction set, and individual qubit stability. These factors determine both the quantum-part execution time and the end-to-end wall clock time relevant for end-users, but also the ability to perform fault-tolerant quantum computation in the future. We end with an overview of which applications have been shown to be well suited for the peculiar properties of neutral atom-based quantum computers.
This is the second paper in a series of papers providing an overview of different quantum computing hardware platforms from an industrial end-user perspective. It follows our first paper on neutral-atom quantum computing. In the present paper, we provide a survey on the current state-of-the-art in trapped-ion quantum computing, taking up again the perspective of an industrial end-user. To this end, our paper covers, on the one hand, a comprehensive introduction to the physical foundations and mechanisms that play an important role in operating a trapped-ion quantum computer. On the other hand, we provide an overview of the key performance metrics that best describe and characterise such a device's current computing capability. These metrics encompass performance indicators such as qubit numbers, gate times and errors, native gate sets, qubit stability and scalability as well as considerations regarding the general qubit types and trap architectures. In order to ensure that these metrics reflect the current state of trapped-ion quantum computing as accurate as possible, they have been obtained by both an extensive review of recent literature and, more importantly, from discussions with various quantum hardware vendors in the field. We combine these factors and provide - again from an industrial end-user perspective - an overview of what is currently possible with trapped-ion quantum computers, which algorithms and problems are especially suitable for this platform, what are the relevant end-to-end wall clock times for calculations, and what might be possible with future fault-tolerant trapped-ion quantum computers.
Abstract Neutral Atom Quantum Computing(NAQC) emerges as a promising hardware platform primarily due to its long coherence times and scalability. Additionally, NAQC offers computational advantages encompassing potential long-range connectivity, native multi-qubit gate support, and the ability to physically rearrange qubits with high fidelity. However, for the successful operation of a NAQC processor, one additionally requires new software tools to translate high-level algorithmic descriptions into a hardware executable representation, taking maximal advantage of the hardware capabilities. Realizing new software tools requires a close connection between tool developers and hardware experts to ensure that the corresponding software tools obey the corresponding physical constraints. This work aims to provide a basis to establish this connection by investigating the broad spectrum of capabilities intrinsic to the NAQC platform and its implications on the compilation process. To this end, we first review the physical background of NAQC and derive how it affects the overall compilation process by formulating suitable constraints and figures of merit. We then provide a summary of the compilation process and discuss currently available software tools in this overview. Finally, we present selected case studies and employ the discussed figures of merit to evaluate the different capabilities of NAQC and compare them between two hardware setups.
Neutral Atom Quantum Computing (NAQC) emerges as a promising hardware platform primarily due to its long coherence times and scalability. Additionally, NAQC offers computational advantages encompassing potential long-range connectivity, native multi-qubit gate support, and the ability to physically rearrange qubits with high fidelity. However, for the successful operation of a NAQC processor, one additionally requires new software tools to translate high-level algorithmic descriptions into a hardware executable representation, taking maximal advantage of the hardware capabilities. Realizing new software tools requires a close connection between tool developers and hardware experts to ensure that the corresponding software tools obey the corresponding physical constraints. This work aims to provide a basis to establish this connection by investigating the broad spectrum of capabilities intrinsic to the NAQC platform and its implications on the compilation process. To this end, we first review the physical background of NAQC and derive how it affects the overall compilation process by formulating suitable constraints and figures of merit. We then provide a summary of the compilation process and discuss currently available software tools in this overview. Finally, we present selected case studies and employ the discussed figures of merit to evaluate the different capabilities of NAQC and compare them between two hardware setups.
Neutral atom qubits are one of the leading approaches for implementation of a large scale quantum computer. The original proposals for neutral atom qubits were formulated more than 25 years ago, with first demonstrations of a universal gate set following 10 years later. In the last few years the performance and scale of neutral atom qubit arrays has developed at a rapid pace leading to demonstrations of quantum algorithms, and logical qubits for fault tolerant error correction. This contribution reviews the physics of the neutral atom approach, surveys current capabilities, and provides an outlook for future progress.
Quantum computing promises to revolutionize several scientific and industrial domains by tackling problems that are intractable for classical supercomputers. At the centre of this effort is the quantum processor unit (QPU), implemented today across multiple physical qubit platforms. This review provides a comparative analysis of the state of quantum processors as of late 2024/early 2025, focusing on superconducting qubits, trapped ions, photonic systems, neutral atoms, silicon spin qubits, and emerging topological approaches. We compile and compare recent processor generations such as IBM’s Heron family, Google’s updated Sycamore-class devices, Quantinuum’s H-series, IonQ’s Aria and Forte, neutral-atom platforms with more than 1,000 trapped atoms, and silicon spin prototypes like Tunnel Falls. Key performance metrics, including qubit count, gate and readout fidelity, coherence time, operation speed, and holistic benchmarks such as Quantum Volume (QV) and Algorithmic Qubits (#AQ) are examined with reference to concrete experimental milestones. We discuss algorithmic capabilities demonstrated on current hardware, early realizations of logical qubits and fault-tolerant primitives, and the distinction between feasibility-oriented “quantum advantage” experiments and emerging signs of practical “quantum utility”. Finally, we outline the main technical bottlenecks for each platform on the path from today’s NISQ devices toward universal fault-tolerant quantum computers.
The pursuit of a universal, fault-tolerant quantum computer has transformed quantum computing from a predominantly theoretical discipline into a rapidly diversifying hardware ecosystem. This review presents a comprehensive and technically grounded analysis of the principal physical qubit modalities: superconducting circuits, trapped ions, photonic platforms, neutral atoms, semiconductor spin qubits, and topological approaches, focusing on their underlying operating principles, performance characteristics, and system-level constraints. We examine how these qubit technologies are embedded within scalable quantum processor architectures, including control and readout infrastructures, connectivity topologies, and quantum error correction strategies. The review provides a comparative study of key performance metrics, such as coherence times, gate fidelities, error rates, and scalability, reveals fundamental trade-offs between speed, robustness, and operational complexity that shape distinct technological roadmaps and target applications. We further highlight the ongoing transition from noisy intermediate-scale quantum (NISQ) devices toward architectures centred on logical qubits, driven by advances in materials engineering, precision control, and quantum information theory. Together, these developments sketch the emerging routes toward fault-tolerant quantum computing and practical quantum advantage, while offering readers a coherent entry point and reference guide to the current quantum hardware landscape.