This brief presents a high-speed quantum random number generator (QRNG) based on the Quantum Random FlipFlop (QRFF) architecture, utilizing two single-photon avalanche diodes (SPADs) per pixel. The design is implemented using the Samsung 28 nm CMOS process. Each pixel integrates a pair of SPAD detectors, following the QRFF model, enabling a significant improvement in output speed compared to conventional QRFF configurations using a single detector. Experimental results demonstrate that a single pixel achieves a throughput of up to 2 Mbps. Furthermore, the generated random numbers successfully pass the NIST statistical test suite without requiring any postprocessing.
This brief presents a high-speed quantum random number generator (QRNG) based on the Quantum Random FlipFlop (QRFF) architecture, utilizing two single-photon avalanche diodes (SPADs) per pixel. The design is implemented using the Samsung 28 nm CMOS process. Each pixel integrates a pair of SPAD detectors, following the QRFF model, enabling a significant improvement in output speed compared to conventional QRFF configurations using a single detector. Experimental results demonstrate that a single pixel achieves a throughput of up to 2 Mbps. Furthermore, the generated random numbers successfully pass the NIST statistical test suite without requiring any postprocessing.
A 16×16 Pixel Post-Processing Free Quantum Random Number Generator Based on SPADs
In this brief, we present a 16 × 16-pixel quantum random number generator (QRNG) based on Single-Photon Avalanche Diodes, implemented in CMOS 150-nm technology. Each pixel consists of two detectors, featuring 17.2 μm ×7.7 μm size, and an arbiter, based on a phase comparator, enhancing the working range of the generator. The QRNG has achieved a random bit efficiency of 90% at a given observation window of 200 ns. The maximum speed is up to 18.2 Mbps for the whole array due to limited readout capability. The measurement result shows the random numbers can pass the standard randomness test without any post-processing.
Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs, there is often little modeling or analytical description of the entropy source, circuit extraction, and post-processing provided. In this work, we present a single-photon avalanche diode (SPAD)-based QRNG design, which utilizes the quantum random flip-flop (QRFF) method. Extensive modeling of detector and circuit imperfections that result in entropy degradation is performed. A new method to analytically model serial autocorrelations of the proposed bit generation method, which includes detector dead time, is proposed. Then, a Verilog-AMS model is developed in order to validate the analytical model in simulation. A novel transistor implementation of the QRFF circuit is presented, which enables compensation of the degradation in entropy inherent to the finite non-symmetric transitions of the random flip-flop. Finally, a full system containing two independent arrays of the QRFF circuit is manufactured and tested in a 55-nm bipolar–CMOS–DMOS (BCD) technology node, demonstrating bit generation statistics that are commensurate to the developed model. The full chip is able to generate 3.3 Gb/s of data when operated with an external LED. Pixelwise and spatial analysis of bias and correlation is performed. NIST STS (SP 800-22) and SP 800-90B are used to benchmark the generated bit strings.
Optical quantum random number generators (QRNGs) are a special class of physical random data sources, whose randomness is established on elementary quantum optics processes. We present a QRNG based on a CMOS chip which overcomes the limitations of the commonly used optical QRNG and which achieves a random bit generation rate up to 200 Mb/s. The CMOS chip is based on an array of single-photon avalanche diodes (SPADs) and digital counters. We prove the absolute randomness of the generated random data through statistical test suites and even more stringent correlation and bias tests applied to 32 Gbit streams. The QRNG passes all tests; hence, it proves to be one of the fastest and more reliable CMOS optical QRNGs currently available.
For globally connected devices like smart phones, personal computers and Internet-of-things devices, the ability to generate random numbers is essential for execution of cryptographic protocols responsible for information security. Generally, a random number generator should be small, robust, utilize as few hardware and energy resources as possible, yet provide excellent randomness at a high enough speed (bitrate) for a given purpose. In this work we present a quantum random number generator (QRNG) which makes use of a photoelectric effect in single-photon avalanche diodes (SPADs) as a source of randomness and is scalable to any desired bitrate. We use the random flip-flop method in which random bits are obtained by periodic sampling of a randomly toggling flip-flop. For the first time we investigate this method in detail and find that, out of two main imperfections, bias is due only to hardware imperfections while autocorrelation predominantly resides with the method itself. SPADs are integrated on a silicon chip together with passive quenching and digital pulse-shaping circuitry, using a standard 180 nm CMOS process. A separate FPGA chip derives random numbers from the detection signals. The basic QRNG cell, made of only two SPADs and a few logic circuits, can generate up to 20 Mbit/s that pass NIST statistical tests without any further postprocessing. This technology allows integration of a QRNG on a single silicon chip using readily available industrial processes.
Quantum random number generators are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs there is often little modelling or analytical description of the entropy source, circuit extraction and post-processing provided. In this work, we first discuss theory on the quantum random flip-flop (QRFF), which elucidates the role of circuit imperfections that manifest themselves in bias and correlation. Then, a Verilog-AMS model is developed in order to validate the analytical model in simulation. A novel transistor implementation of the QRFF circuit is presented, which enables compensation of the degradation in entropy inherent to the finite non-symmetric transitions of the random flip-flop. Finally, a full system containing two independent arrays of the QRFF circuit is manufactured and tested in a 55 nm Bipolar-CMOS-DMOS (BCD) technology node, demonstrating bit generation statistics that are commensurate to the developed model. The full chip is able to generate 3.3 Gbps of data when operated with an external LED, whereas an individual QRFF can generate 25 Mbps each of random data while maintaining a Shannon entropy bound > 0.997, which is one of the highest per pixel bit generation rates to date. NIST STS is used to benchmark the generated bit strings, thereby validating the QRFF circuit as an excellent candidate for fully-integrated QRNGs.
Experimental demonstration of a quantum random number generator based on one single-photon avalanche diode (SPAD) detector, a T / ( T − t ) pulse-shaped laser, and an field-programmable gate array (FPGA) acquisition module is presented. An integrated laser driver drives an external laser diode at 670 nm wavelength, whereas the SPAD with a photon detection probability of 18.5% is integrated together with an active quenching-resetting circuit. The SPAD detector generates counts for the interarrival time (IAT) measurement system implemented in an FPGA, where the change of the IATs between consecutive pulses is used to derive a random bit stream. It is shown how the application of a pulse-shaped laser driver can increase the performance of the system as compared to the continuous-wave operation of the laser diode to achieve the maximum generation rate of 5 Mbps while using a single SPAD. The generated numbers pass all randomness tests of the National Institute of Standards and Technology (NIST), Dieharder, and ENT test (pseudorandom number sequence test) suits.