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IEEE National Aerospace and Electronics Conference (NAECON)

Implementing Grover’s Algorithm on NISQ Chips

Reece Robertson, Colburn Riffel, Matthew Slodov, Peter Hendrickson

Published Jul 28, 2025• 0 citations
Publisher

Abstract

This paper explores the performance of proof-of-concept scale instances of Grover’s algorithm, analyzing execution on several fully-connected trapped-ion and pairwise-connected superconducting quantum hardware devices. Only trapped-ion devices outperformed sampling from a uniform distribution across all possible outputs.
DOI
10.1109/naecon65708.2025.11235338

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Abstract Quantum search algorithm (also known as Grover's algorithm) lays the foundation for many other quantum algorithms. Although it is very simple, its implementation is limited on noisy intermediate-scale quantum (NISQ) processors. Grover's algorithm was designed without considering the physical resources, such as depth, in the real implementations. Therefore, Grover's algorithm can be improved for NISQ devices. In this paper, we demonstrate how to implement quantum search algorithms better on NISQ devices. We present detailed benchmarks of the five-qubit quantum search algorithm on different quantum processors, including IBMQ, IonQ, and Honeywell quantum devices. We report the highest success probability of the five-qubit search algorithm compared to previous works. Our results show that designing the error-aware quantum search algorithms is possible, which can maximally harness the power of NISQ computers.
This work tests the performance of Grover’s search circuits on some IBM superconducting quantum devices in case of the size of search space N = 16 and N = 32. Ideally, we expect to get an outcome probability distribution that is clearly peaked at the goal (marked) state. However, the quantum circuit executed on real devices is vulnerable to noise which leads to fluctuations in the results. The contributions of this paper are therefore the following: a) it presents two new Grover’s search circuits for N = 16 which were not yet reported in the state of the art; b) it shows performance difference between simulation results and results obtained on real devices; c) it shows the need of adding error correction on the circuit for N ≥ 32.
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