This article presents a cryogenic CMOS receiver operating across 4.7–7.9 GHz for frequency-division multiplexing (FDM) quantum state readout. The designed receiver employs a double quadrature (DQ) architecture and a hybrid poly-phase filter (PPF) is proposed to achieve an impressive image rejection ratio (IRR) to meet the 99.99% higher fidelity requirements in quantum error correction (QEC). In addition, gain tuning at different stages of the low noise amplifier (LNA) facilitates a broadband gain and flatness, while the subsequent receiver chains of a broadband mixer and an improved four-input intermediate frequency amplifier (IF-AMP) provide further gain compensation. Fabricated with a standard 55-nm CMOS technology, the LNA achieves a measured power gain of 27.4 dB, with a −3-dB bandwidth (BW) of 5.2 GHz at 6 K. The measured cryogenic noise figure (NF) ranges from 0.79 to 1 dB consuming merely 5.5 mW from a 1.2-V supply. Overall receiver measurements demonstrate a peak gain of 48.2 dB, a −5-dB flatness of 3.2 GHz, and an IRR that exceeds 40 dB at 6 K. These results demonstrate the receiver’s capacity for high-fidelity qubits’ state readout.
This work introduces a broadband cryogenic receiver for scalable multiplexed readout of qubits. The receiver utilizes a double quadrature architecture with amplitude and phase error suppression. The hybrid poly-phase filter (PPF) is applied in the architecture to further reduce the input amplitude and phase errors at the radio frequency (RF) end, enhancing the circuit's overall error vector magnitude (EVM). To address the issue of wide bandwidth (BW) for qubit expansion, a low noise amplifier (LNA) with broadband input and noise matching and an improved four-input intermediate frequency amplifier (IF-AMP) with a resistance feedback structure are proposed, achieving a broadband gain response with high flatness. The chip has been designed in standard 55 nm CMOS technology. The LNA achieves a measured power gain of 27.4 dB at 5 GHz with a -3 dB BW of 5.2 GHz at 6 K. Across the entire band of interest, the measured noise figure (NF) deviates by just 0.15 dB from the minimum noise figure (NFmin) and less than 2 dB at 300K, while the measured cryogenic NF falls within the range of 0.79-1 dB. The LNA consumes only 5.5 mW from a 1.2 V supply. Simulation results of the designed receiver indicate that it delivers an average gain of 49.5 dB with a -3 dB BW of 2.4 GHz and an image rejection ratio (IRR) exceeding 40 dB at 300 K.
This letter presents an ultrawideband cryogenic low-noise amplifier (LNA) with current reuse and stacked inverter-based input-referred noise (IRN) cancellation in 40-nm CMOS. The first stage utilizes an IRN reduction high-
Qgate inductor with current reuse, a stacked inverter-based shunt-resistive feedback input stage, and a cryogenically aware back-gate biasing technique to regulate the threshold voltage under cryogenic operation. The second stage is the common-source (CS) main amplifier, followed by a cascode current-reuse auxiliary amplifier to suppress the channel thermal noise of the main amplifier. The third stage is the current-reuse CS inverter-based postamplifier buffer stage. At 4 K, the LNA achieves a measured peak gain (
S21) of 37 dB, with a large 3-dB bandwidth (BW) from 0.15 to 8 GHz and aNFminof 0.4 dB at 3.2 GHz under
PDCof 13.2 mW. To our knowledge, the proposed LNA achieves the BW bandwidth and the figure of merit (FoM) among the highest compared to published CMOS LNAs operating at 4 K. The proposed LNA is suitable for both spin and superconducting qubit readout.
A cryogenic low-voltage, broadband low-noise amplifier(LNA) has been designed for qubit state readout systems. The proposed LNA utilizes passive components for noise cancellation. A tri-coupled transformer is utilized to simultaneously achieve broadband input impedance matching and noise matching. Additionally, it incorporates capacitive feedback and an in-phase transformer to effectively cancel noise. Implemented in 28-nm bulk CMOS technology and verified at 10 K, the LNA achieves a maximum gain of 26.7 dB, a −3-dB bandwidth of 2.2 GHz, a lowest noise temperature (NT) of 25 K, a power consumption of 4.05 mW at 0.6-V supply voltage, and a figure of merit (FoM) of 0.12 dB/mW/ph, which is comparable with the recent works.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at
3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of
10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at
3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be
<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion,
4 K receiver for qubit readout that achieves
>1.9GHz of IF bandwidth with
>50 dB conversion gain and
0.7 dB NF while consuming only
17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing
3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
In quantum computers, the quantum state discrimination of the physical quantum bits (Qubits) occupies ~80% of the quantum error correction (QEC) cycle. The RF reflectometry or dispersive readout determines the Qubit state by monitoring the RF reflection of the attached high-Q resonant tank. Compared to their dc counterparts, the RF reflectometers enjoy a high signal-to-noise ratio (SNR), low drifting, and fast speed. As a result, a high-fidelity, single-shot, scalable reflectometer array based on cryogenic CMOS (Cryo-CMOS) ICs is in demand for the future large-scale Qubit array (
103∼106Qubits). However, the classic Cryo-CMOS heterodyne reflectometers, consisting of MOSFET-based LNA, mixer, and baseband blocks, suffer from high noise temperature and dc power. To address these issues, the Cryo-CMOS parametric circuitry based on varactors is explored. In this article, a dual-Qubit homodyne reflectometer array with 2 RX channels and 1 TX channel is demonstrated. In the RX, the degenerate parametric amplifier (DPA) enjoys a Q-enhanced,
λRF/2differential-mode (DM) resonator for the high-gain parametric amplification. The common mode (CM) RF input of DPA interacts with the DM resonator by a nonreciprocal, dynamic mode coupling (DMC). It eliminates the necessity of a circulator and the potential oscillation of DPA. The scalability challenge of the DPA’s noise temperature
Tnoiseversus the environment temperature
Tenvis also investigated. In the TX, a current-mode logic (CML) divider with interstate locking and a vector modulator (VM) is implemented to achieve fast modulation for the spur and noise rejection. Measured at 4.2 K, the implemented 65 nm Cryo-CMOS chip presents a
4.5∼7GHz bandwidth, 52 dB peak RF gain, and 78 K noise temperature, and generates a 10 MHz TX pulse train with -22 dBm RF power and 30 dB tunability. It consumes a total dc power of 33 mW.