Abstract Design space exploration (DSE) plays an important role in optimising quantum circuit execution by systematically evaluating different configurations of compilation strategies and hardware settings. In this paper, we conduct a comprehensive investigation into the impact of various layout methods, qubit routing techniques, and optimisation levels, as well as device-specific properties such as different variants and strengths of noise and imperfections, the topological structure of qubits, connectivity densities, and back-end sizes. By spanning through these dimensions, we aim to understand the interplay between compilation choices and hardware characteristics. A key question driving our exploration is whether the optimal selection of device parameters, mapping techniques, comprising of initial layout strategies and routing heuristics can mitigate device induced errors beyond standard error mitigation approaches. Our results show that carefully selecting software strategies (e.g., mapping and routing algorithms) and tailoring hardware characteristics (such as minimising noise and leveraging topology and connectivity density) significantly improve the fidelity of circuit execution outcomes, and thus the expected correctness or success probability of the computational result. We provide estimates based on key metrics such as circuit depth, gate count and expected fidelity. Our results highlight the importance of hardware–software co-design, particularly as quantum systems scale to larger dimensions, and along the way towards fully error corrected quantum systems: Our study is based on computationally noisy simulations, but considers various implementations of quantum error correction (QEC) using the same approach as for other algorithms. The observed sensitivity of circuit fidelity to noise and connectivity suggests that co-design principles will be equally critical when integrating QEC in future systems. Our exploration provides practical guidelines for co-optimising physical mapping, qubit routing, and hardware configurations in realistic quantum computing scenarios.
Abstract Design space exploration (DSE) plays an important role in optimising quantum circuit execution by systematically evaluating different configurations of compilation strategies and hardware settings. In this paper, we conduct a comprehensive investigation into the impact of various layout methods, qubit routing techniques, and optimisation levels, as well as device-specific properties such as different variants and strengths of noise and imperfections, the topological structure of qubits, connectivity densities, and back-end sizes. By spanning through these dimensions, we aim to understand the interplay between compilation choices and hardware characteristics. A key question driving our exploration is whether the optimal selection of device parameters, mapping techniques, comprising of initial layout strategies and routing heuristics can mitigate device induced errors beyond standard error mitigation approaches. Our results show that carefully selecting software strategies (e.g., mapping and routing algorithms) and tailoring hardware characteristics (such as minimising noise and leveraging topology and connectivity density) significantly improve the fidelity of circuit execution outcomes, and thus the expected correctness or success probability of the computational result. We provide estimates based on key metrics such as circuit depth, gate count and expected fidelity. Our results highlight the importance of hardware–software co-design, particularly as quantum systems scale to larger dimensions, and along the way towards fully error corrected quantum systems: Our study is based on computationally noisy simulations, but considers various implementations of quantum error correction (QEC) using the same approach as for other algorithms. The observed sensitivity of circuit fidelity to noise and connectivity suggests that co-design principles will be equally critical when integrating QEC in future systems. Our exploration provides practical guidelines for co-optimising physical mapping, qubit routing, and hardware configurations in realistic quantum computing scenarios.
Design space exploration (DSE) plays an important role in optimising quantum circuit execution by systematically evaluating different configurations of compilation strategies and hardware settings. In this work, we study the impact of layout methods, qubit routing techniques, compiler optimization levels, and hardware-specific properties, including noise characteristics, topological structures, connectivity densities, and device sizes. By traversing these dimensions, we aim to understand how compilation choices interact with hardware features. A central question in our study is whether carefully selected device parameters and mapping strategies, including initial layouts and routing heuristics, can mitigate hardware-induced errors beyond standard error mitigation methods. Our results show that choosing the right software strategies (e.g., layout and routing) and tailoring hardware properties (e.g., reducing noise or leveraging connectivity) significantly enhances the fidelity of quantum circuit executions. We provide performance estimates using metrics such as circuit depth, gate count, and expected fidelity. These findings highlight the value of hardware-software co-design, especially as quantum systems scale and move toward error-corrected computing. Our simulations, though noisy, include quantum error correction (QEC) scenarios, revealing similar sensitivities to layout and connectivity. This suggests that co-design principles will be vital for integrating QEC in future devices. Overall, we offer practical guidance for co-optimizing mapping, routing, and hardware configuration in real-world quantum computing.
Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.
Quantum computing is poised to revolutionize computational paradigms by leveraging quantum mechanics principles such as superposition and entanglement.However, the full-scale deployment of quantum applications remains constrained by hardware limitations, including high error rates and quantum decoherence.Quantum Software Engineering (QSE) emerges as a critical field addressing these challenges by optimizing algorithm design, error mitigation, and compiler strategies to enhance fault tolerance.Algorithm design in QSE focuses on developing quantum algorithms that efficiently exploit quantum parallelism while minimizing resource overhead.Key advancements include quantum variational algorithms, hybrid quantum-classical frameworks, and novel quantum heuristics tailored for optimization and cryptographic problems.Error mitigation techniques play a pivotal role in extending quantum circuit reliability without requiring full quantum error correction.Methods such as zero-noise extrapolation, probabilistic error cancellation, and quantum embedding techniques help reduce computational inaccuracies.Additionally, compiler optimization ensures efficient quantum program execution by minimizing gate depth, optimizing qubit mapping, and leveraging noise-adaptive scheduling to enhance quantum hardware performance.This paper explores the synergy between these three pillars of QSE, analyzing their impact on improving the feasibility of fault-tolerant quantum computing.It also examines emerging trends, including AI-driven quantum compilers, adaptive error mitigation techniques, and hardware-aware quantum software development.By bridging the gap between theoretical advancements and practical implementations, QSE provides a structured approach to accelerating quantum computing adoption across domains such as cryptography, materials science, and artificial intelligence.The findings underscore the necessity of interdisciplinary collaboration in developing robust quantum software solutions that maximize computational efficiency while mitigating inherent quantum hardware limitations.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
Quantum computing, leveraging the principles of superposition and entanglement, holds the potential to revolutionize computational problem-solving across a wide array of fields, from cryptography to complex system simulations. However, unlocking the full power of quantum computing requires the development of advanced quantum compilation techniques that can efficiently map high-level algorithms onto physical quantum hardware. This paper delves into state-of-the-art optimization strategies within quantum compilers, with a particular focus on methods such as Relaxed Peephole Optimization (RPO), gate reordering techniques for the Quantum Approximate Optimization Algorithm (QAOA), and reinforcement learning (RL)-driven frameworks. It also explores innovative approaches like distributed quantum compilation, parity quantum optimization, and the Paulihedral framework, all designed to minimize gate counts, reduce circuit depth, and optimize overall resource utilization. A key contribution of this work is the introduction of error mitigation techniques that enhance the fidelity and scalability of quantum circuits, particularly on noisy intermediate-scale quantum (NISQ) devices. Through comprehensive empirical evaluations across a variety of quantum algorithms, the paper demonstrates significant improvements in critical performance metrics such as circuit depth, gate count, and execution efficiency, providing a promising direction for optimizing quantum circuit design tailored to diverse quantum hardware platforms.
The transition from noisy intermediate-scale quantum (NISQ) processors to large-scale fault-tolerant machines requires more than incremental improvements in physical qubit fidelity. While advances in quantum error correction (QEC) theory continue to lower the theoretical overhead of quantum computing, much of this research remains abstracted from the physical realities of qubit implementations. This disconnect often results in hardware-agnostic designs that are inefficient or impractical to build. In this dissertation, I identify three primary gaps between theoretical QEC research and practical hardware: (1) the high levels of noise and temporal instability in experimental devices that impede scalable QEC; (2) the prohibitively large qubit and time costs of useful algorithms, driven largely by the limitations of the standard surface code; and (3) the failure of current resource estimates to account for hardware-level constraints, such as limited connectivity and the complexity of implementing non-local operations. To bridge these gaps, I propose a holistic, cross-stack approach where the error correction protocols and the physical hardware are designed in concert. By developing realistic device models and hardware-aware solutions at the lowest levels of the software stack, we can accelerate the path toward functional fault-tolerance. I present my work across three research thrusts: first, leveraging codesign to mitigate hardware-specific noise and reduce physical error rates; second, developing software tools for fault-tolerant quantum computers to reduce the space-time overhead of the QEC layer; and third, proposing two novel hardware-aware QEC architectures that provide practical, high-performance routes to scalable quantum computation.