An important step in developing multi-qubit gates is to construct efficient benchmarking protocols for them. In our previous paper (arXiv: 2210.04330), we developed metrological protocols to measure the reduced Choi matrix i.e., the completely positive (CP) maps induced on a subset S of the qubits, by the multi-qubit gate. Here, we show a set of classically verifiable properties that the Choi matrix satisfies if it is a reduction of a multi-qubit unitary and use them to develop benchmarks. We identify three types of errors that affect the implementation of a multi-qubit unitary, based on their mathematical properties and physical origin. Although a target multi-qubit gate is a unitary operator, errors turn it into a general completely positive (CP) map. Errors due to coupling to a thermal bath result in the multi-qubit gate being CP-divisible (Markovian), deviating from a unitary. The reduced Choi matrix of a multi-qubit gate has a property known as double stochasticity, which is violated in the presence of Markovian errors. We construct a benchmark using double-stochasticity violation and show that it is sensitive to coupling to any thermal bath at a finite temperature. Further, errors due to shot-to-shot fluctuations result in a non-markovian, i.e., CP-indivisible quantum process. We prove a new property, which we call the \rank property of the reduced Choi matrix, the violation of which implies a CP-indivisible error. A third category of errors comes from systematics in the implementation of a multi-qubit gate, resulting in no deviation from unitarity. We refer to this as unitary errors. This corresponds to the most challenging type of error to benchmark. We develop a partial-benchmarking protocol for such errors using symmetries of the multi-qubit gate being applied.An important step in developing multi-qubit gates is to construct efficient benchmarking protocols for them. In our previous paper (arXiv: 2210.04330), we developed metrological protocols to measure the reduced Choi matrix i.e., the completely positive (CP) maps induced on a subset S of the qubits, by the multi-qubit gate. Here, we show a set of classically verifiable properties that the Choi matrix satisfies if it is a reduction of a multi-qubit unitary and use them to develop benchmarks. We identify three types of errors that affect the implementation of a multi-qubit unitary, based on their mathematical properties and physical origin. Although a target multi-qubit gate is a unitary operator, errors turn it into a general completely positive (CP) map. Errors due to coupling to a thermal bath result in the multi-qubit gate being CP-divisible (Markovian), deviating from a unitary. The reduced Choi matrix of a multi-qubit gate has a property known as double stochasticity, which is violated in the presence of Markovian errors. We construct a benchmark using double-stochasticity violation and show that it is sensitive to coupling to any thermal bath at a finite temperature. Further, errors due to shot-to-shot fluctuations result in a non-markovian, i.e., CP-indivisible quantum process. We prove a new property, which we call the \rank property of the reduced Choi matrix, the violation of which implies a CP-indivisible error. A third category of errors comes from systematics in the implementation of a multi-qubit gate, resulting in no deviation from unitarity. We refer to this as unitary errors. This corresponds to the most challenging type of error to benchmark. We develop a partial-benchmarking protocol for such errors using symmetries of the multi-qubit gate being applied.

arXiv:2301.07109Jan 17, 20230 citations

Matrix Representation of Arbitrarily Controlled Quantum Gates

Marco Lewis, Paolo Zuliani, Sadegh Soudjani

arXiv:2205.02525Jan 1, 20220 citations

Quantum Matrices Using Quantum Gates

Manu Mitra

Jan 1, 20180 citations

Benchmarking multi-qubit gates -- I: Metrological aspects

Bharath Hebbe Madhusudhana

Accurate and precise control of large quantum systems is paramount to achieve practical advantages on quantum devices. Therefore, benchmarking the hardware errors in quantum computers has drawn significant attention lately. Existing benchmarks for digital quantum computers involve averaging the global fidelity over a large set of quantum circuits and are therefore unsuitable for specific multi-qubit gates used in analog quantum operations. Moreover, average global fidelity is not the optimal figure-of-merit for some of the applications specific to multi-qubit gates and analog devices , such as the study of many-body physics, which often use local observables. In this two-part paper, we develop a new figure-of-merit suitable for multi-qubit quantum gates based on the reduced Choi matrix of the operation. In the first part, we develop an efficient, scalable protocol to completely characterize the reduced Choi matrix. We identify two sources of sampling errors in measurements of the reduced Choi matrix and we show that there are fundamental limits to the rate of convergence of the sampling errors, analogous to the standard quantum limit and Heisenberg limit. A slow convergence rate of sampling errors would mean that we need a large number of experimental shots. We develop protocols using quantum information scrambling, which has been observed in disordered systems for e.g., to speed up the rate of convergence of the sampling error at state preparation Moreover, we develop protocols using squeezed and entangled initial states to enhance the convergence rate of the sampling error at measurement, which results in a metrologically enhanced reduced process tomography protocol.Accurate and precise control of large quantum systems is paramount to achieve practical advantages on quantum devices. Therefore, benchmarking the hardware errors in quantum computers has drawn significant attention lately. Existing benchmarks for digital quantum computers involve averaging the global fidelity over a large set of quantum circuits and are therefore unsuitable for specific multi-qubit gates used in analog quantum operations. Moreover, average global fidelity is not the optimal figure-of-merit for some of the applications specific to multi-qubit gates and analog devices , such as the study of many-body physics, which often use local observables. In this two-part paper, we develop a new figure-of-merit suitable for multi-qubit quantum gates based on the reduced Choi matrix of the operation. In the first part, we develop an efficient, scalable protocol to completely characterize the reduced Choi matrix. We identify two sources of sampling errors in measurements of the reduced Choi matrix and we show that there are fundamental limits to the rate of convergence of the sampling errors, analogous to the standard quantum limit and Heisenberg limit. A slow convergence rate of sampling errors would mean that we need a large number of experimental shots. We develop protocols using quantum information scrambling, which has been observed in disordered systems for e.g., to speed up the rate of convergence of the sampling error at state preparation Moreover, we develop protocols using squeezed and entangled initial states to enhance the convergence rate of the sampling error at measurement, which results in a metrologically enhanced reduced process tomography protocol.

arXiv:2210.04330Oct 9, 20220 citations

Matrix Quantum Computing and Matrix Quantum Information

Badis Ydri

Aug 12, 20260 citations

A quantum neural network framework for scalable quantum circuit approximation of unitary matrices

Rohit Sarma Sarkar, Bibhas Adhikari

In this paper, we develop a Lie group theoretic approach for parametric representation of unitary matrices. This leads to develop a quantum neural network framework for quantum circuit approximation of multi-qubit unitary gates. Layers of the neural networks are defined by product of exponential of certain elements of the Standard Recursive Block Basis, which we introduce as an alternative to Pauli string basis for matrix algebra of complex matrices of order $2^n$ . The recursive construction of the neural networks implies that the quantum circuit approximation is scalable i.e. quantum circuit for an $(n+1)$ -qubit unitary can be constructed from the circuit of $n$ -qubit system by adding a few CNOT gates and single-qubit gates.In this paper, we develop a Lie group theoretic approach for parametric representation of unitary matrices. This leads to develop a quantum neural network framework for quantum circuit approximation of multi-qubit unitary gates. Layers of the neural networks are defined by product of exponential of certain elements of the Standard Recursive Block Basis, which we introduce as an alternative to Pauli string basis for matrix algebra of complex matrices of order $2^n$. The recursive construction of the neural networks implies that the quantum circuit approximation is scalable i.e. quantum circuit for an $(n+1)$-qubit unitary can be constructed from the circuit of $n$-qubit system by adding a few CNOT gates and single-qubit gates.

arXiv:2405.00012Feb 7, 20242 citations

2^n

. The recursive construction of the neural networks implies that the quantum circuit approximation is scalable i.e. quantum circuit for an

(n+1)

-qubit unitary can be constructed from the circuit of

n

-qubit system by adding a few CNOT gates and single-qubit gates.