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IEEE/CIC International Conference on Communications in China (ICCC)

An Improved Full Rank Condition for Nonbinary LDPC Codes over BI-AWGN Channel

Yuhao Liu, Qin Huang

Published Aug 10, 2025• 0 citations
Publisher

Abstract

This paper improves the full rank condition (FRC) to construct nonbinary LDPC codes for binary AWGN channels, in which there is usually a one-bit error in one erroneous symbol. When assigning values to symbols in a cycle, our improved FRC condition not only considers rank deficiency, but also prefers values with the smallest probability that the related checks are mistakenly satisfied due to one-bit errors in these symbols. Finally, we present the IFRC-based optimization algorithm performs row-wise optimization on the non-zero elements of the parity-check matrix. Simulation results show the effectiveness of IFRC compared to FRC: the error-correcting performance is improved by 0.1dB to 0.5dB, and the error floor can be reduced by up to an order of magnitude.

DOI
10.1109/icccworkshops67136.2025.11148204

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This paper improves the full rank condition (FRC) to construct nonbinary LDPC codes for binary AWGN channels, in which there is usually a one-bit error in one erroneous symbol. When assigning values to symbols in a cycle, our improved FRC condition not only considers rank deficiency, but also prefers values with the smallest probability that the related checks are mistakenly satisfied due to one-bit errors in these symbols. Finally, we present the IFRC-based optimization algorithm performs row-wise optimization on the non-zero elements of the parity-check matrix. Simulation results show the effectiveness of IFRC compared to FRC: the error-correcting performance is improved by 0.1dB to 0.5dB, and the error floor can be reduced by up to an order of magnitude.
Short cycles in a nonbinary low-density parity-check (NB-LDPC) code may be even more harmful to its performance if they do not satisfy the so-called full rank condition (FRC). This is because they may induce low-weight codewords or absorbing sets in that case. Thus, it is important to count the number of short cycles not satisfying the FRC as well as the number of short cycles for analyzing the performance of an NB-LDPC code. In this paper, we first develop a novel message-passing algorithm and identify how it is related to the FRC. We then propose a low-complexity algorithm for counting the number of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short cycles. Finally, we propose a low-complexity algorithm for designing an NB-LDPC code with low error floor. Depending on the modulation scheme, the codes constructed by the proposed design algorithm have similar or slightly worse performance, compared with those constructed via the method by Poulliat et al. However, the proposed design algorithm does not require a cycle enumeration algorithm with high complexity, and therefore is feasible even in the case of large code length, say ≥5000.
In this paper, an improved full rank condition (named as λ-FRC) is proposed for the construction of nonbinary LDPC codes. Compared with the conventional FRC, the λ-FRC introduces a metric λ to evaluate the reliability of the messages passing through the circle. Codes with better performance can be obtained by selecting elements of the parity matrix according to the metric. Based on the λ-FRC, a greedy search algorithm is proposed to design the codes efficiently. In order to further improve the performance of the codes constructed, an iterative search algorithm is applied in the construction. Simulation results show that the performance of codes constructed by the λ-FRC methods outperforms those by the FRC methods, and the iterative search algorithm improves the performance of the codes as the iteration number increases1.
Trapping sets with short cycles are known to give a detrimental effect on the error floor performance of a low-density parity-check (LDPC) code. Unlike in binary LDPC codes., short cycles in a nonbinary low-density parity-check (NB-LDPC) code may be even more harmful to its performance if they do not satisfy the so-called full rank condition (FRC). This is because they may induce low-weight codewords or absorbing sets in that case. Thus, it is crucial to count the number of short cycles not satisfying the FRC as well as the number of short cycles for analyzing the performance of an NB-LDPC code. In this paper, we first develop a novel message-passing algorithm and identify how it is related to the FRC. We then propose a low-complexity algorithm for counting the number of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short cycles.
Short or moderate-length non-binary low-density parity-check (NB-LDPC) codes have the potential applications in future low latency and high-reliability communication thanks to the strong error correction capability and parallel decoding. Because of the existence of the error floor, the NB-LDPC codes usually cannot satisfy very low bit error rate (BER) requirements. In this paper, a low-complexity method is proposed for optimizing the minimum distance of the NB-LDPC code in a progressive chord edge growth manner. Specifically, each chord edge connecting two non-adjacent vertices is added to the Hamiltonian cycle one-by-one. For each newly added chord edge, the configuration of non-zero entries corresponding to the chord edge is determined according to the so-called full rank condition (FRC) of all cycles that are related to the chord edge in the obtained subgraph. With minor modifications to the designed method, it can be used to construct the NB-LDPC codes with an efficient encoding structure. The analysis results show that the method for designing NB-LDPC codes while using progressive chord edge growth has lower complexity than traditional methods. The simulation results show that the proposed method can effectively improve the performance of the NB-LDPC code in the high signal-to-noise ratio (SNR) region. While using the proposed scheme, an NB-LDPC code with a quite low BER can be constructed with extremely low complexity.
In this paper, we focus on short-block nonbinary LDPC (NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDPC codes. Notice that the parity-check matrix H of the resulting code is square and not of full rank, and its row weight and column weight are the same. By replacing the ones in the same column of H with a nonzero element of finite fields GF(q), a class of NB-LDPC codes over GF(q) is obtained. Numerical results show that the constructed codes perform well over the AWGN channel and have fast decoding convergence. Therefore, the proposed NB-LDPC codes provide a promising coding scheme for low-latency and high-reliability communications.
In this paper, we propose a simple mathematical structure to improve the BER (bit error rate) performance of quasi-cyclic low-density parity-check (QC-LDPC) codes. Since the proposed structure can be defined in-between those of random codes and structured codes, these proposed QC-LDPC codes not only perform as well as random-LDPC codes, but also preserve the advantage of structured LDPC codes which is easier to implement over coding hardware. Moreover, the proposed structure, constructed from balanced incomplete block design (BIBD), can reduce the density of parity-check matrix and hence reduce the number of short cycles, which generally lead to better performance. At the end, we show that the error floor performance of QC-LDPC codes can be improved by proposed hybrid structures and perform well over binary-input additive white Gaussian noise (BI-AWGN) channel.