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Physics

Scaling Quantum-Dot-Qubit Systems

Nathaniel C. Bishop

Published Apr 30, 2025• 0 citations
Publisher
DOI
10.1103/physics.18.88

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Abstract Scaling up spin qubits in silicon-based quantum dots is one of the pivotal challenges in achieving large-scale semiconductor quantum computation. To satisfy the connectivity requirements and reduce the lithographic complexity, utilizing the qubit array structure and the circuit quantum electrodynamics (cQED) architecture together is expected to be a feasible scaling scheme. A triple-quantum dot (TQD) coupled with a superconducting resonator is regarded as a basic cell to demonstrate this extension scheme. In this article, we investigate a system consisting of a silicon TQD and a high-impedance TiN coplanar waveguide (CPW) resonator. The TQD can couple to the resonator via the right double-quantum dot (RDQD), which reaches the strong coupling regime with a charge–photon coupling strength of g 0/(2π) = 175 MHz. Moreover, we illustrate the high tunability of the TQD through the characterization of stability diagrams, quadruple points (QPs), and the quantum cellular automata (QCA) process. Our results contribute to fostering the exploration of silicon-based qubit integration.
The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.