Abstract The first hardware evidence is reported that a Quantum Memory Matrix (QMM) ‐ conceived as a Planck‐scale lattice of finite‐dimensional memory cells ‐ functions as an ultra‐shallow, measurement‐free error‐suppression layer for noisy intermediate‐scale quantum processors. On a seven‐qubit IBM transmon device, quantum states are imprint onto local cells with single‐qubit and nearest‐neighbor gates and later retrieve them through a controlled‐SWAP, guaranteeing unitary reversibility. A single imprint–retrieval cycle attains a hardware fidelity of ; prepending the same layer to a conventional repetition code boosts the logical fidelity to ‐ a 32 % improvement obtained without additional CX gates. Incorporating the layer into a variational quantum classifier lowers the final training loss by 35 % and halves run‐to‐run variance, evidencing its value for hybrid quantum‐classical workloads. Noise‐calibrated simulations further show that stacking three QMM layers brings the logical error rate to within 20 % of a distance‐three surface code while using an order of magnitude fewer qubits. Because the QMM booster is fully unitary and eschews mid‐circuit measurement, it is directly compatible with platforms where rapid stabilizer read‐out is impractical and provides empirical support for the broader notion that space‐time itself may behave as a distributed quantum memory.
Abstract The first hardware evidence is reported that a Quantum Memory Matrix (QMM) ‐ conceived as a Planck‐scale lattice of finite‐dimensional memory cells ‐ functions as an ultra‐shallow, measurement‐free error‐suppression layer for noisy intermediate‐scale quantum processors. On a seven‐qubit IBM transmon device, quantum states are imprint onto local cells with single‐qubit and nearest‐neighbor gates and later retrieve them through a controlled‐SWAP, guaranteeing unitary reversibility. A single imprint–retrieval cycle attains a hardware fidelity of ; prepending the same layer to a conventional repetition code boosts the logical fidelity to ‐ a 32 % improvement obtained without additional CX gates. Incorporating the layer into a variational quantum classifier lowers the final training loss by 35 % and halves run‐to‐run variance, evidencing its value for hybrid quantum‐classical workloads. Noise‐calibrated simulations further show that stacking three QMM layers brings the logical error rate to within 20 % of a distance‐three surface code while using an order of magnitude fewer qubits. Because the QMM booster is fully unitary and eschews mid‐circuit measurement, it is directly compatible with platforms where rapid stabilizer read‐out is impractical and provides empirical support for the broader notion that space‐time itself may behave as a distributed quantum memory.
Abstract Quantum computing has recently emerged as a novel paradigm for solving problems otherwise intractable on classical computers, yet the practical progress of quantum computers is severely impacted by noise, decoherence, and imperfect gate operations in Noisy Intermediate-Scale Quantum (NISQ) devices. Specific to IBM Quantum hardware, imperfections due to readout error, gate errors, and device drift, which depends on time, resolves limits for the accuracy of outputs from our algorithms. The mitigation strategies currently used, for example, Measurement Error Mitigation (MEM), Zero Noise Extrapolation (ZNE), and Clifford Data Regression (CDR), offer improvement over raw, unmitigated outputs, but they are static and not dynamic; the reduction of noise in within an NISQ device is temporal and can vary in patterns that are non-zero. In addition to this, using the conventional methods provides inconsistent and suboptimal results.This study will provide enhanced reliability with respect to performing quantum computation on IBM Quantum hardware with a unique mitigation framework that is adaptive and computationally efficient for a high-fidelity output. The problem taken on here is the failure of existing error mitigation strategies to provide adaptive noise compensation, as they assume a statically-distributed error, despite the performance-related characteristics already being documented in regards to calibration drift and variation over time.To achieve this, we propose a Hybrid Adaptive Error Mitigation (HAEM) approach that includes baseline measurement error mitigation and an additional correction layer that utilizes realtime calibration information, along with lightweight machine learning models. The approach can be broken down into three steps: (i) perform standard measurement error mitigation to reduce classical readout noise, (ii) execute compact calibration circuits, such as Bell states, GHZ states and Clifford benchmarks to capture then current error profile of the device, and (iii) use a lightweight machine learning model (having been trained on historical and newest calibration data) to dynamically change the mitigation weights applied for the target quantum algorithm. All implementation is done using Qiskit Runtime to ensure low-latency execution, and we completed experiments on both Qiskit Aer noisy simulators and IBM Quantum devices.Initial results suggest HAEM improved the outputs of quantum algorithms' fidelity compared to the unmitigated runs and the baseline measurement error mitigation (MEM) runs. On the noisy simulators, HAEM increased fidelity from a raw performance of 0.65 to 0.87, nearly a 34% improvement. In fairer hardware-like scenarios, fidelity-on-average was persistently 12% better than MEM, with nearly equal time duration for the additional adaptive measurements. The adaptive aspect of HAEM consistently supported subsequent calibration cycles of the device and was effective to continue providing fidelity improvements despite the static mitigation performance degrading.To sum up, the proposed HAEM framework is a modern and viable alternative for error mitigation which brings together the benefits of baseline approaches with corrections that are driven by fixed-function error-corrective, adaptive learning. As both learning-based and standard baseline approaches can only achieve fixed levels of performance, HAEM, through its use of noise mitigation both at execution time and through correlating it with standard data, provides a route towards reliable quantum computations on current IBM hardware. HAEM also presents a contribution to the NISQ error-resilient landscape, and however it is intended that it will continue to improve future applications of hybrid workflows of quantum and classical computation where error mitigation and resilience is important.
To solve problems of practical importance1,2, quantum computers probably need to incorporate quantum error correction, in which a logical qubit is redundantly encoded in many noisy physical qubits3–5. The large physical-qubit overhead associated with error correction motivates the search for more hardware-efficient approaches6–18. Here, using a superconducting quantum circuit19, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance d = 5 (ref. 10). A stabilizing circuit passively protects cat qubits against bit flips20–24. The repetition code, using ancilla transmons for syndrome measurement, corrects cat qubit phase flips. We study the performance and scaling of the logical qubit memory, finding that the phase-flip correcting repetition code operates below the threshold. The logical bit-flip error is suppressed with increasing cat qubit mean photon number, enabled by our realization of a cat-transmon noise-biased CX gate. The minimum measured logical error per cycle is on average 1.75(2)% for the distance-3 code sections, and 1.65(3)% for the distance-5 code. Despite the increased number of fault locations of the distance-5 code, the high degree of noise bias preserved during error correction enables comparable performance. These results, where the intrinsic error suppression of the bosonic encodings enables us to use a hardware-efficient outer error-correcting code, indicate that concatenated bosonic codes can be a compelling model for reaching fault-tolerant quantum computation. Bosonic qubits can be engineered to feature intrinsic protection against certain kinds of errors, which makes quantum error correction across many bosonic qubits possible with less overhead.
We present a general framework for applying linear quantum error mitigation (QEM) techniques directly to physical qubits within a logical qubit to suppress logical errors. By exploiting the linearity of quantum error correction (QEC), we demonstrate that any linear QEM method$\unicode{x2014}$including probabilistic error cancellation (PEC), zero-noise extrapolation (ZNE), and symmetry verification$\unicode{x2014}$can be integrated into the physical layer without requiring modifications to the subsequent QEC decoder. Applying this framework to memory experiments using PEC, we analytically prove and numerically verify that the leading-order contribution to the logical error can be removed, increasing the effective code distance by 2. Our simulations on repetition and rotated surface codes show that a distance-3 code with physical-level PEC achieves logical error rates lower than or similar to a distance-5 unmitigated code while using 40% and 64% fewer qubits, respectively. These results establish physical-level QEM as a widely compatible and resource-efficient strategy for enhancing logical performance in early fault-tolerant architectures.
Abstract The accumulation of physical errors 1–3 prevents the execution of large-scale algorithms in current quantum computers. Quantum error correction 4 promises a solution by encoding k logical qubits onto a larger number n of physical qubits, such that the physical errors are suppressed enough to allow running a desired computation with tolerable fidelity. Quantum error correction becomes practically realizable once the physical error rate is below a threshold value that depends on the choice of quantum code, syndrome measurement circuit and decoding algorithm 5 . We present an end-to-end quantum error correction protocol that implements fault-tolerant memory on the basis of a family of low-density parity-check codes 6 . Our approach achieves an error threshold of 0.7% for the standard circuit-based noise model, on par with the surface code 7–10 that for 20 years was the leading code in terms of error threshold. The syndrome measurement cycle for a length- n code in our family requires n ancillary qubits and a depth-8 circuit with CNOT gates, qubit initializations and measurements. The required qubit connectivity is a degree-6 graph composed of two edge-disjoint planar subgraphs. In particular, we show that 12 logical qubits can be preserved for nearly 1 million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of 0.1%, whereas the surface code would require nearly 3,000 physical qubits to achieve said performance. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.
Quantum error correction [1, 2, 3, 4] provides a path to reach practical quantum computing by combining multiple physical qubits into a logical qubit, where the logical error rate is suppressed exponentially as more qubits are added. However, this exponential suppression only occurs if the physical error rate is below a critical threshold. Here, we present two below-threshold surface code memories on our newest generation of superconducting processors, Willow: a distance-7 code, and a distance-5 code integrated with a real-time decoder. The logical error rate of our larger quantum memory is suppressed by a factor of Λ=2.14±0.02 when increasing the code distance by two, culminating in a 101-qubit distance-7 code with 0.143% ± 0.003% error per cycle of error correction. This logical memory is also beyond break-even, exceeding its best physical qubit’s lifetime by a factor of 2.4±0.3 . Our system maintains below-threshold performance when decoding in real time, achieving an average decoder latency of 63 μs at distance-5 up to a million cycles, with a cycle time of 1.1 μs. We also run repetition codes up to distance-29 and find that logical performance is limited by rare correlated error events occurring approximately once every hour, or 3×109 cycles. Our results present device performance that, if scaled, could realize the operational requirements of large scale fault-tolerant quantum algorithms.
Readout errors are one of the dominant sources of noise in current quantum processors, limiting both expectation-value estimation and sampling-based applications. Since they affect only the classical measurement outcomes, they can be addressed using classical coding techniques: immediately before measurement, each data qubit is redundantly encoded with ancilla qubits, and the resulting bit string is decoded either by post-selection or by majority voting. Unlike conventional readout error mitigation, which corrects only aggregate quantities such as expectation values, this approach operates on individual measurement shots and can therefore produce approximately corrected samples. We present a systematic cross-platform and cross-generation experimental evaluation of repetition-code readout error detection and correction. We benchmark the same protocol on IBM Heron r1-r3 superconducting processors and Quantinuum H1 and H2 trapped-ion processors while independently varying the code distance, hardware generation, and encoding layout. We find that both error detection and correction improve readout fidelity on every device and generation tested, even as the unencoded baseline improves substantially across successive hardware releases. At the same time, the value of additional redundancy depends strongly on the underlying hardware. On superconducting processors, the extra gate errors introduced by the encoding rapidly offset its benefits, whereas on trapped-ion processors the much lower gate error rates allow larger code distances to remain advantageous.