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ICTACT Journal on Data Science and Machine Learning

CODING SCHEME IN NETWORKS USING QUASI CYCLIC LOW DENSITY PARITY CHECK CODES GENERATION WITH SVM

Jayasri Subramaniam, Kousik Nalliyanna Goundar Veerappan

Published Sep 1, 2024• 0 citations
Publisher

Abstract

Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes are highly effective error correction codes due to their structured sparsity, providing low complexity and superior error performance. However, improving their performance with modern classification techniques remains a challenge. This study integrates Support Vector Machine (SVM) generation with QC-LDPC codes to optimize error correction efficiency. The proposed approach combines the robust coding properties of QC-LDPC codes with SVM’s decision boundary characteristics, enhancing decoding accuracy. Simulation results show that for a code length of 1024 bits, the Bit Error Rate (BER) improved by 15%, while the Frame Error Rate (FER) reduced by 10% compared to traditional QC-LDPC methods. These improvements underscore the potential of SVMs in refining error correction processes for communication systems, particularly in scenarios with high noise interference.

DOI
10.21917/ijdsml.2024.0144

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Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes are highly effective error correction codes due to their structured sparsity, providing low complexity and superior error performance. However, improving their performance with modern classification techniques remains a challenge. This study integrates Support Vector Machine (SVM) generation with QC-LDPC codes to optimize error correction efficiency. The proposed approach combines the robust coding properties of QC-LDPC codes with SVM’s decision boundary characteristics, enhancing decoding accuracy. Simulation results show that for a code length of 1024 bits, the Bit Error Rate (BER) improved by 15%, while the Frame Error Rate (FER) reduced by 10% compared to traditional QC-LDPC methods. These improvements underscore the potential of SVMs in refining error correction processes for communication systems, particularly in scenarios with high noise interference.
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An improved combining method for designing quasi- cyclic low- density parity- check( QC-LDPC) codes based on Chinese Remainder Theorem( CRT) is proposed to improve the error- correcting performance by increasing the girth and decreasing the number of short cycles. With the CRT combining method,the difficult problem of designing QC- LDPC codes with girth g is translated into a task of designing one component code with girth g. By properly permuting the column blocks of parity- check matrices of other component codes,a lot of QC- LDPC codes with much shorter cycles and better performance can be designed,which are more suitable for communication systems with request of high reliability. Simulations show that compared with existing CRT- based QC- LDPC codes,the proposed QC- LDPC codes have much shorter cycles and obtain 1. 2 d B coding gain at bit error rate( BER) of 10- 6.
Techniques for searching for good quasi-cyclic (QC) LDPC block codes of short and moderate lengths which are suitable for practical purposes are studied. To facilitate implementations only codes whose parity-check matrices having bidiagonal structure of their submatrices and consequently having low encoding complexity are considered. The problem of finding QC LDPC codes with the near-optimum frame or bit error rate performance is split into two independent steps: searching for the near-optimum column degree distribution of the parity-check matrix together with the best base matrix for this degree distribution and searching for the near-optimum labeling of the chosen base matrix. Sets of parameters and criteria for both steps are introduced and discussed. They allow further reduction of the search complexity without significant loss of the search optimality. New QC LDPC block codes of various code rates are obtained and their BER and FER performances are compared with those of the LDPC block codes as well as the turbo codes defined in the IEEE 802.16 WiMAX standard.
Quasi Cyclic Low Density Parity Check codes (QC-LDPC) is proposed to reduce the complexity of the Low Density Parity Check codes (LDPC) further while obtaining the similar performance. Our proposed QC-LDPC presents an improved construction of circulant sub-matrices based QC-LDPC at high SNR. The proposed construction yields a performance gain of about 1 dB at a 0.0003 bit error rate (BER). Proposed code is tested on 4 types of decoding algorithm and compared. Proposed algorithm is also compared with the existing QC-LDPC and the proposed approach outperforms the existing one at high SNR. Simulation is also performed varying the number of horizontal submatrix and the result shows that the parity check matrix with smaller horizontal concatenation shows better performance.
Low-density parity check (LDPC) codes, are a family of error-correcting codes, their performances close to the Shannon limit make them very attractive solutions for digital communication systems. There are several algorithms for decoding LDPC codes that show great diversity in terms of performance related to error correction. Also, very recently, many research papers involved the genetic algorithm (GA) in coding theory, in particular, in the decoding linear block codes case, which has heavily contributed to reducing the bit error rate (BER). In this paper, an efficient method based on the GA is proposed and it is used to improve the power of correction in terms of BER and the frame error rate (FER) of LDPC codes. Subsequently, the proposed algorithm can independently decide the most suitable moment to stop the decoding process, moreover, it does not require channel information (CSI) making it adaptable for all types of channels with different noise or intensity. The simulations show that the proposed algorithm is more efficient in terms of BER compared to other LDPC code decoders.
In this paper, we propose a simple mathematical structure to improve the BER (bit error rate) performance of quasi-cyclic low-density parity-check (QC-LDPC) codes. Since the proposed structure can be defined in-between those of random codes and structured codes, these proposed QC-LDPC codes not only perform as well as random-LDPC codes, but also preserve the advantage of structured LDPC codes which is easier to implement over coding hardware. Moreover, the proposed structure, constructed from balanced incomplete block design (BIBD), can reduce the density of parity-check matrix and hence reduce the number of short cycles, which generally lead to better performance. At the end, we show that the error floor performance of QC-LDPC codes can be improved by proposed hybrid structures and perform well over binary-input additive white Gaussian noise (BI-AWGN) channel.