The throughput of the error correction decoding is one of the major bottlenecks of high-speed continuous-variable quantum key distribution (CV-QKD) systems and an integrated decoder with Gbps decoding throughput is implemented in this work.
The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
The throughput of error correction is the main bottleneck of continuous variable quantum key distribution (CV-QKD) postprocessing. Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA with limited precision can improve the decoding throughput significantly. However, the limited precision on FPGA results in the existence of residual error-bits after decoding, which lowers the secret key rate and restricts the application of high-rate real-time CVQKD system. In this paper, an efficient decoding scheme is proposed to erase the residual error-bits and decrease the frame errors rate (FER), where the decoding process into two stages and some values of initial Log Likelihood Ratio (LLR) are adjusted according to the proposed principles before starting the second-stage decoding. For the rates 0.2 and 0.1 LDPC codes, numerical results demonstrate that the proposed decoding scheme decreases the FER obviously and the throughputs of 152.47Mbps and 88.32Mbps are achieved, which can be applied to support high-speed CV-QKD system under transmission distance of 25km and 50km respectively.
More than Mbps secret key rate was demonstrated for continuous-variable quantum key distribution (CV-QKD) systems, but real-time postprocessing is not allowed, which is restricted by the throughput of the error correction decoding in postprocessing. In this paper, a high-throughput FPGA-based quasi-cyclic LDPC decoder is proposed and implemented to support Mbps real-time secret key rate generation for CV-QKD for the first time. A residual bit error correction algorithm is used to solve the problem of high frame errors rate (FER) caused by the limited precision of the decoder. Specifically, real-time high-speed decoding for CV-QKD systems with typical code rates 0.2 and 0.1 is implemented on a commercial FPGA, and two throughputs of 360.92Mbps and 194.65Mbps are achieved, respectively, which can support 17.97 Mbps and 2.48 Mbps real-time generation of secret key rates under typical transmission distances of 25km and 50km, correspondingly. The proposed method paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
Throughput of error correction is the bottleneck of the postprocessing for continuous-variable quantum key distribution system. In this paper, a shuffled iterative decoding method is proposed to reduce the number of iterations for error correction. For three typical code rate, i.e., 0.1, 0.05, 0.02, our results show that the maximum decoding speed is up to 72.86 Mbits/s, 53.96 Mbits/s and 42.45 Mbits/s, respectively, which significantly improves the real-time processing capacity of continuous-variable quantum key distribution system.
The decoding throughput during post-processing is one of the major bottlenecks that occur in a continuous-variable quantum key distribution (CV-QKD) system. In this paper, we propose a layered decoder to decode quasi-cyclic multi-edge type LDPC (QC-MET-LDPC) codes using a graphics processing unit (GPU) in continuous-variable quantum key distribution (CV-QKD) systems. As described herein, we optimize the storage methods related to the parity check matrix, merge the sub-matrices which are unrelated, and decode multiple codewords in parallel on the GPU. Simulation results demonstrate that the average decoding speed of LDPC codes with three typical code rates, i.e., 0.1, 0.05 and 0.02, is up to 64.11 Mbits/s, 48.65 Mbits/s and 39.51 Mbits/s, respectively, when decoding 128 codewords of length [Formula: see text] simultaneously without early termination.
This paper addresses the high-throughput requirements of information reconciliation in continuous-variable quantum key distribution (CV-QKD) systems by proposing an FPGA-based quasi-cyclic low-density parity-check (QC-LDPC) decoder implementation utilizing cross-layer scheduling. Through a preprocessing approach involving base matrix row reordering and data merging, the scheme effectively resolves memory access conflicts in layered decoding, enabling conflict-free parallel processing. Operating at 250 MHz, the decoder achieves a throughput of 100.5 Mbps, representing a 20% improvement over conventional approaches while maintaining equivalent frame error rate performance.