Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

SPIE Conference on Quantum and Nonlinear Optics

High-throughput error correction for continuous-variable quantum key distribution systems based on shuffled iterative decoding

Yang Li, Bingjie Xu, Li Ma, Jie Yang, Wei Huang, Heng Wang, Yujie Luo

Published Oct 9, 2020• 1 citation
Publisher

Abstract

Throughput of error correction is the bottleneck of the postprocessing for continuous-variable quantum key distribution system. In this paper, a shuffled iterative decoding method is proposed to reduce the number of iterations for error correction. For three typical code rate, i.e., 0.1, 0.05, 0.02, our results show that the maximum decoding speed is up to 72.86 Mbits/s, 53.96 Mbits/s and 42.45 Mbits/s, respectively, which significantly improves the real-time processing capacity of continuous-variable quantum key distribution system.

DOI
10.1117/12.2574960

Related papers

An efficient and high-speed two-stage decoding scheme for continuous-variable quantum key distribution system

Chuang Zhou, Yang Li, Li Ma +7 more

The throughput of error correction is the main bottleneck of continuous variable quantum key distribution (CV-QKD) postprocessing. Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA with limited precision can improve the decoding throughput significantly. However, the limited precision on FPGA results in the existence of residual error-bits after decoding, which lowers the secret key rate and restricts the application of high-rate real-time CVQKD system. In this paper, an efficient decoding scheme is proposed to erase the residual error-bits and decrease the frame errors rate (FER), where the decoding process into two stages and some values of initial Log Likelihood Ratio (LLR) are adjusted according to the proposed principles before starting the second-stage decoding. For the rates 0.2 and 0.1 LDPC codes, numerical results demonstrate that the proposed decoding scheme decreases the FER obviously and the throughputs of 152.47Mbps and 88.32Mbps are achieved, which can be applied to support high-speed CV-QKD system under transmission distance of 25km and 50km respectively.

SPIE Conference on Quantum and Nonlinear Optics•Nov 27, 2022•2 citations

High speed error correction for continuous-variable quantum key distribution with multi-edge type LDPC code

Xiangyu Wang, Yichen Zhang, Song Yu +1 more

Abstract Error correction is a significant step in postprocessing of continuous-variable quantum key distribution system, which is used to make two distant legitimate parties share identical corrected keys. We propose an experiment demonstration of high speed error correction with multi-edge type low-density parity check (MET-LDPC) codes based on graphic processing unit (GPU). GPU supports to calculate the messages of MET-LDPC codes simultaneously and decode multiple codewords in parallel. We optimize the memory structure of parity check matrix and the belief propagation decoding algorithm to reduce computational complexity. Our results show that GPU-based decoding algorithm greatly improves the error correction speed. For the three typical code rate, i.e., 0.1, 0.05 and 0.02, when the block length is 10 6 and the iteration number are 100, 150 and 200, the average error correction speed can be respectively achieved to 30.39 Mbits/s (over three times faster than previous demonstrations), 21.23 Mbits/s and 16.41 Mbits/s with 64 codewords decoding in parallel, which supports high-speed real-time continuous-variable quantum key distribution system.

arXiv:1711.01783•Scientific Reports•Jul 6, 2018•69 citations

High-throughput decoder of quasi-cyclic LDPC codes with limited precision for continuous-variable quantum key distribution systems

Chuang Zhou, Yang Li, Ma Li +7 more

More than Mbps secret key rate was demonstrated for continuous-variable quantum key distribution (CV-QKD) systems, but real-time postprocessing is not allowed, which is restricted by the throughput of the error correction decoding in postprocessing. In this paper, a high-throughput FPGA-based quasi-cyclic LDPC decoder is proposed and implemented to support Mbps real-time secret key rate generation for CV-QKD for the first time. A residual bit error correction algorithm is used to solve the problem of high frame errors rate (FER) caused by the limited precision of the decoder. Specifically, real-time high-speed decoding for CV-QKD systems with typical code rates 0.2 and 0.1 is implemented on a commercial FPGA, and two throughputs of 360.92Mbps and 194.65Mbps are achieved, respectively, which can support 17.97 Mbps and 2.48 Mbps real-time generation of secret key rates under typical transmission distances of 25km and 50km, correspondingly. The proposed method paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.

arXiv:2207.01860•Jul 5, 2022•5 citations

A high-throughput and FPGA-based LDPC decoder for continuous-variable quantum key distribution system

Chuang Zhou, Li Yang, Li Ma +6 more

The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.

SPIE Conference on Quantum and Nonlinear Optics•Oct 12, 2023•3 citations

Integrated high-performance LDPC decoder for Continuous-Variable Quantum Key Distribution System

Chuang Zhou, Yang Li, Li Ma +4 more

The throughput of the error correction decoding is one of the major bottlenecks of high-speed continuous-variable quantum key distribution (CV-QKD) systems and an integrated decoder with Gbps decoding throughput is implemented in this work.

Optical Fiber Communication Conference•Jan 1, 2025•0 citations

A novel error correction protocol for continuous variable quantum key distribution

Kadir Gümüş, Tobias A. Eriksson, Masahiro Takeoka +4 more

Reconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.

Scientific Reports•May 17, 2021•19 citations
Throughput of error correction is the bottleneck of the postprocessing for continuous-variable quantum key distribution system. In this paper, a shuffled iterative decoding method is proposed to reduce the number of iterations for error correction. For three typical code rate, i.e., 0.1, 0.05, 0.02, our results show that the maximum decoding speed is up to 72.86 Mbits/s, 53.96 Mbits/s and 42.45 Mbits/s, respectively, which significantly improves the real-time processing capacity of continuous-variable quantum key distribution system.
The throughput of error correction is the main bottleneck of continuous variable quantum key distribution (CV-QKD) postprocessing. Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA with limited precision can improve the decoding throughput significantly. However, the limited precision on FPGA results in the existence of residual error-bits after decoding, which lowers the secret key rate and restricts the application of high-rate real-time CVQKD system. In this paper, an efficient decoding scheme is proposed to erase the residual error-bits and decrease the frame errors rate (FER), where the decoding process into two stages and some values of initial Log Likelihood Ratio (LLR) are adjusted according to the proposed principles before starting the second-stage decoding. For the rates 0.2 and 0.1 LDPC codes, numerical results demonstrate that the proposed decoding scheme decreases the FER obviously and the throughputs of 152.47Mbps and 88.32Mbps are achieved, which can be applied to support high-speed CV-QKD system under transmission distance of 25km and 50km respectively.
Abstract Error correction is a significant step in postprocessing of continuous-variable quantum key distribution system, which is used to make two distant legitimate parties share identical corrected keys. We propose an experiment demonstration of high speed error correction with multi-edge type low-density parity check (MET-LDPC) codes based on graphic processing unit (GPU). GPU supports to calculate the messages of MET-LDPC codes simultaneously and decode multiple codewords in parallel. We optimize the memory structure of parity check matrix and the belief propagation decoding algorithm to reduce computational complexity. Our results show that GPU-based decoding algorithm greatly improves the error correction speed. For the three typical code rate, i.e., 0.1, 0.05 and 0.02, when the block length is 10 6 and the iteration number are 100, 150 and 200, the average error correction speed can be respectively achieved to 30.39 Mbits/s (over three times faster than previous demonstrations), 21.23 Mbits/s and 16.41 Mbits/s with 64 codewords decoding in parallel, which supports high-speed real-time continuous-variable quantum key distribution system.
More than Mbps secret key rate was demonstrated for continuous-variable quantum key distribution (CV-QKD) systems, but real-time postprocessing is not allowed, which is restricted by the throughput of the error correction decoding in postprocessing. In this paper, a high-throughput FPGA-based quasi-cyclic LDPC decoder is proposed and implemented to support Mbps real-time secret key rate generation for CV-QKD for the first time. A residual bit error correction algorithm is used to solve the problem of high frame errors rate (FER) caused by the limited precision of the decoder. Specifically, real-time high-speed decoding for CV-QKD systems with typical code rates 0.2 and 0.1 is implemented on a commercial FPGA, and two throughputs of 360.92Mbps and 194.65Mbps are achieved, respectively, which can support 17.97 Mbps and 2.48 Mbps real-time generation of secret key rates under typical transmission distances of 25km and 50km, correspondingly. The proposed method paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
Reconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.