Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEICE Transactions on Electronics

MarginX: Simple and Fast Circuit Parameter Optimization Tool for Superconductor Circuits

Sho MATSUOKA, Nobuyuki Yoshikawa, Yuki Yamanashi

Published May 27, 2025• 3 citations
Publisher

Abstract

For integrated circuit design, optimizing circuit parameters is crucial to achieve wide operating margins and high yields, even in the presence of fluctuations and variations in device characteristics. In this paper, we report the development of a new circuit parameter optimization tool for superconductor integrated circuits, leveraging the latest analog circuit simulator and the center of gravity method. The developed optimization tool, implemented in C++, utilizes a parallel processing algorithm for highspeed optimization. By using only the phase information of the Josephson junction to distinguish the correct behavior of the circuit, this tool can be applied not only to conventional single flux quantum (SFQ) circuits but also to superconductor circuits whose behavior is not based on a 2π phase change. We optimized several SFQ logic gates and compared the margin expansion and optimization time with conventional optimization tools. Our tool achieved an optimization time of less than 2% of that of conventional tools in most cases. This optimization tool facilitates the rapid parameter optimization of any superconductor circuits containing various types of Josephson junctions.

DOI
10.1587/transele.2024ecp5100

Related papers

Optimization of Half-Flux-Quantum Circuits Composed of π-Shift and Conventional Josephson Junctions

Shoma Tanemura, Yuto Takeshita, Feng Li +3 more

We report optimization of half-flux-quantum (HFQ) circuits composed of SQUIDs containing conventional Josephson junctions and π-shift magnetic Josephson junctions. The SQUID can act as a Josephson junction with an extremely small critical current and be easily switched by a weak driving force with the assistance of the circulating current that is induced due to the π-shift and quantization conditions. It leads to a drastic reduction of both static and dynamic power consumption. However, the parameter margins of the HFQ circuits obtained so far is narrow compared with conventional single-flux-quantum circuits. Since HFQ circuits use many circuit elements and require the two junctions in the SQUID to switch alternately and symmetrically, circuit parameter optimization is much more difficult. In this study, we developed an optimization tool for HFQ circuits, including operation judgment and margin calculation. We improved the critical margin of the HFQ Josephson transmission line to 39%. We also optimized the HFQ splitter, confluence buffer, and D flip-flop. We discuss design guidelines for HFQ circuits based on our systematic exploration of the optimized circuit parameter sets. We suggest that the optimized loop inductances are around 0.5 and 1.5 of Φ0/2 for data transmission and storage, respectively.

IEEE Transactions on Applied Superconductivity•Mar 17, 2023•15 citations

Automated Verification and Optimization of SFQ Superconducting Circuits

Andrew Haslam, Kurt English, Alexander Derrickson +1 more

New tools have been created to allow a superconducting design flow for schematic design, verification, and optimization. These tools integrate with the Cadence design environment. In single flux quantum superconducting electronics, individual component values, such as wire inductances, Josephson junction critical currents, and bias currents, must be optimized to allow for maximum deviance from the designer value, which is also known as the device margin. One tool is used to create a description of the proper circuit behavior. Included with this tool is the ability to automatically create the description from a Cadence netlist. The other tool is an automated device margin circuit schematic verification and optimization tool, which widens device margins while maintaining proper circuit behavior derived from the first tool. Additionally, this optimization tool can automatically correct the circuit schematic using the proper circuit behavior description. In this paper, the functionality of the language used to create the description of the proper circuit behavior is presented. Several circuits are then verified and optimized based on their correct behavior.

IEEE Access•Jan 1, 2019•3 citations

Logic Operation of HTS SFQ Logic Family

Koji Tsubone, Y. Tarutani, H. Wakana +2 more

A high-Tcsuperconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve Icx uniformity. As a result, all circuits were successfully tested and show at least plusmn40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using YBa2Cu3O7-deltaramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.

IEEE Transactions on Applied Superconductivity•Jul 15, 2009•2 citations

Superconductor digital circuits with π junctions alone

Feng Li, Yuto Takeshita, Masamitsu Tanaka +1 more

We adopt superconductor/ferromagnet/insulator/superconductor (SFIS) Josephson junctions (JJs) as both switching JJs and intrinsic π phase shifters in superconductor digital circuits. The critical current density (Jc) and characteristic voltage (Vc) of the SFIS junctions are about 22 A/cm2 and 22 μV, respectively. The intrinsic π phase shift is confirmed by measuring the suppressed nominal critical current Icn and half-period-shifted modulation pattern of a π–π–π superconducting quantum interference device (SQUID) that contains three π-JJs in a superconducting loop. A single-flux-quantum (SFQ) circuit composed of a DC/SFQ, Josephson transmission line (JTL), and SFQ/DC converter based on SFIS JJs alone is demonstrated at 4.2 K. The energy dissipation of the SFQ/DC converter decreases by 80% because some JJs are self-biased by the π phase shifter. The intrinsic circulating currents induced by the π phase shifters lead to a narrow bias margin (±5%) and even error function, which can be solved by parameters optimization or circuit initialization in the future. The half-modulation period (Φ0/2) of a half-flux-quantum (HFQ) SQUID (a partial HFQ JTL) exhibits propagation of HFQ between π–π–π SQUIDs, indicating that more complex HFQ circuits can be developed with π-JJs alone in the future.

Applied Physics Letters•Apr 17, 2023•10 citations

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits

Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi

Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is required. In this paper, we propose a new timing-aware circuit description method which can be used for SFQ circuit design. Based on the description and the dedicated algorithms we have been developing for SFQ logic circuit design, we propose an integrated design flow for SFQ logic circuits. We have designed a circuit using our developed design tools along with the design flow and demonstrated the correct operation.

IEICE Transactions on Electronics•Jan 1, 2014•14 citations

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Yuki Yamanashi, Sotaro Nakaishi, Nobuyuki Yoshikawa

We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of introduction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The designed flip-flops and logic gates have wide operating margins, the dc-bias margins of larger than ±30%, and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs.

IEEE Transactions on Applied Superconductivity•Mar 18, 2019•11 citations
For integrated circuit design, optimizing circuit parameters is crucial to achieve wide operating margins and high yields, even in the presence of fluctuations and variations in device characteristics. In this paper, we report the development of a new circuit parameter optimization tool for superconductor integrated circuits, leveraging the latest analog circuit simulator and the center of gravity method. The developed optimization tool, implemented in C++, utilizes a parallel processing algorithm for highspeed optimization. By using only the phase information of the Josephson junction to distinguish the correct behavior of the circuit, this tool can be applied not only to conventional single flux quantum (SFQ) circuits but also to superconductor circuits whose behavior is not based on a 2π phase change. We optimized several SFQ logic gates and compared the margin expansion and optimization time with conventional optimization tools. Our tool achieved an optimization time of less than 2% of that of conventional tools in most cases. This optimization tool facilitates the rapid parameter optimization of any superconductor circuits containing various types of Josephson junctions.
We report optimization of half-flux-quantum (HFQ) circuits composed of SQUIDs containing conventional Josephson junctions and π-shift magnetic Josephson junctions. The SQUID can act as a Josephson junction with an extremely small critical current and be easily switched by a weak driving force with the assistance of the circulating current that is induced due to the π-shift and quantization conditions. It leads to a drastic reduction of both static and dynamic power consumption. However, the parameter margins of the HFQ circuits obtained so far is narrow compared with conventional single-flux-quantum circuits. Since HFQ circuits use many circuit elements and require the two junctions in the SQUID to switch alternately and symmetrically, circuit parameter optimization is much more difficult. In this study, we developed an optimization tool for HFQ circuits, including operation judgment and margin calculation. We improved the critical margin of the HFQ Josephson transmission line to 39%. We also optimized the HFQ splitter, confluence buffer, and D flip-flop. We discuss design guidelines for HFQ circuits based on our systematic exploration of the optimized circuit parameter sets. We suggest that the optimized loop inductances are around 0.5 and 1.5 of Φ0/2 for data transmission and storage, respectively.
New tools have been created to allow a superconducting design flow for schematic design, verification, and optimization. These tools integrate with the Cadence design environment. In single flux quantum superconducting electronics, individual component values, such as wire inductances, Josephson junction critical currents, and bias currents, must be optimized to allow for maximum deviance from the designer value, which is also known as the device margin. One tool is used to create a description of the proper circuit behavior. Included with this tool is the ability to automatically create the description from a Cadence netlist. The other tool is an automated device margin circuit schematic verification and optimization tool, which widens device margins while maintaining proper circuit behavior derived from the first tool. Additionally, this optimization tool can automatically correct the circuit schematic using the proper circuit behavior description. In this paper, the functionality of the language used to create the description of the proper circuit behavior is presented. Several circuits are then verified and optimized based on their correct behavior.
A high-Tcsuperconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve Icx uniformity. As a result, all circuits were successfully tested and show at least plusmn40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using YBa2Cu3O7-deltaramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.
We adopt superconductor/ferromagnet/insulator/superconductor (SFIS) Josephson junctions (JJs) as both switching JJs and intrinsic π phase shifters in superconductor digital circuits. The critical current density (Jc) and characteristic voltage (Vc) of the SFIS junctions are about 22 A/cm2 and 22 μV, respectively. The intrinsic π phase shift is confirmed by measuring the suppressed nominal critical current Icn and half-period-shifted modulation pattern of a π–π–π superconducting quantum interference device (SQUID) that contains three π-JJs in a superconducting loop. A single-flux-quantum (SFQ) circuit composed of a DC/SFQ, Josephson transmission line (JTL), and SFQ/DC converter based on SFIS JJs alone is demonstrated at 4.2 K. The energy dissipation of the SFQ/DC converter decreases by 80% because some JJs are self-biased by the π phase shifter. The intrinsic circulating currents induced by the π phase shifters lead to a narrow bias margin (±5%) and even error function, which can be solved by parameters optimization or circuit initialization in the future. The half-modulation period (Φ0/2) of a half-flux-quantum (HFQ) SQUID (a partial HFQ JTL) exhibits propagation of HFQ between π–π–π SQUIDs, indicating that more complex HFQ circuits can be developed with π-JJs alone in the future.
Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is required. In this paper, we propose a new timing-aware circuit description method which can be used for SFQ circuit design. Based on the description and the dedicated algorithms we have been developing for SFQ logic circuit design, we propose an integrated design flow for SFQ logic circuits. We have designed a circuit using our developed design tools along with the design flow and demonstrated the correct operation.
We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of introduction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The designed flip-flops and logic gates have wide operating margins, the dc-bias margins of larger than ±30%, and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs.