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Asia-pacific Journal of Convergent Research Interchange

A Case Study on the Effects of Mid-Circuit Measurements and Qubit Reuse for Quantum Circuit Optimization

SangWon Min, JungSoo Rhee

Published Feb 27, 2025• 0 citations
Publisher

Abstract

To optimize quantum computing performance, it is essential to reduce circuit complexity and minimize resource costs.In particular, mid-circuit measurement and qubit reuse techniques are highly effective in reducing the number of ancillary qubits in algorithms with repetitive operations.This study analyzes how the application of mid-circuit measurement and qubit reuse techniques affects circuit performance, using the Quantum Ripple Carry Adder (QRCA) as an example, which involves numerous repetitive tasks.For this purpose, the QRCA circuit was evaluated in terms of size, depth, and the number of ancillary qubits after applying these techniques.Experimental results showed that in conventional QRCA circuits, the number of ancillary qubits increases with the input size.However, when mid-circuit measurement and qubit reuse techniques were applied, the number of ancillary qubits remained fixed, effectively reducing from O(n) to O(1).Nonetheless, it was observed that this reduction in ancillary qubits increased circuit depth and size.These findings suggest a trade-off between qubit count, circuit depth, and size must be comprehensively considered to select the optimal circuit design.This research aims to contribute to the efficient implementation of optimized quantum circuits by appropriately utilizing mid-circuit measurement and qubit reuse techniques in algorithms that require maximum utilization of limited qubit resources.

DOI
10.47116/apjcri.2025.02.42

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To optimize quantum computing performance, it is essential to reduce circuit complexity and minimize resource costs.In particular, mid-circuit measurement and qubit reuse techniques are highly effective in reducing the number of ancillary qubits in algorithms with repetitive operations.This study analyzes how the application of mid-circuit measurement and qubit reuse techniques affects circuit performance, using the Quantum Ripple Carry Adder (QRCA) as an example, which involves numerous repetitive tasks.For this purpose, the QRCA circuit was evaluated in terms of size, depth, and the number of ancillary qubits after applying these techniques.Experimental results showed that in conventional QRCA circuits, the number of ancillary qubits increases with the input size.However, when mid-circuit measurement and qubit reuse techniques were applied, the number of ancillary qubits remained fixed, effectively reducing from O(n) to O(1).Nonetheless, it was observed that this reduction in ancillary qubits increased circuit depth and size.These findings suggest a trade-off between qubit count, circuit depth, and size must be comprehensively considered to select the optimal circuit design.This research aims to contribute to the efficient implementation of optimized quantum circuits by appropriately utilizing mid-circuit measurement and qubit reuse techniques in algorithms that require maximum utilization of limited qubit resources.
A number of commercially available quantum computers, such as those based on trapped-ion or superconducting qubits, can now perform mid-circuit measurements and resets.In addition to being crucial for quantum error correction, this capability can help reduce the number of qubits needed to execute many types of quantum algorithms by measuring qubits as early as possible, resetting them, and reusing them elsewhere in the circuit.In this work, we introduce the idea of qubit-reuse compilation, which takes as input a quantum circuit and produces as output a compiled circuit that requires fewer qubits to execute due to qubit reuse.We present two algorithms for performing qubit-reuse compilation: an exact constraint programming optimization model and a greedy heuristic.We introduce the concept of dual circuits, obtained by exchanging state preparations with measurements and vice versa and reversing time, and show that optimal qubit-reuse compilation requires the same number of qubits to execute a circuit as its dual.We illustrate the performance of these algorithms on a variety of relevant near-term quantum circuits, such as one-dimensional and two-dimensional time-evolution circuits, and numerically benchmark their performance on the quantum adiabatic optimization algorithm (QAOA) applied to the MaxCut problem on random three-regular graphs.To demonstrate the practical benefit of these techniques, we experimentally realize an 80-qubit QAOA MaxCut circuit on the 20-qubit Quantinuum H1-1 trapped-ion quantum processor using qubit-reuse compilation algorithms.
Quantum measurement is important to quantum computing as it extracts the outcome of the circuit at the end of the computation. Previously, all measurements have to be done at the end of the circuit. Otherwise, it will incur significant errors. But it is not the case now. Recently IBM started supporting dynamic circuits through hardware (instead of software by simulator). With mid-circuit hardware measurement, we can improve circuit efficacy and fidelity from three aspects: (a) reduced qubit usage, (b) reduced swap insertion, and (c) improved fidelity. We demonstrate this using real-world applications Bernstein Verizani on real hardware and show that circuit resource usage can be improved by 60\%, and circuit fidelity can be improved by 15\%. We design a compiler-assisted tool that can find and exploit the tradeoff between qubit reuse, fidelity, gate count, and circuit duration. We also developed a method for identifying whether qubit reuse will be beneficial for a given application. We evaluated our method on a representative set of essential applications. We can reduce resource usage by up to 80\% and circuit fidelity by up to 20\%.
Qubit capacity is a common bottleneck in quantum computers, limiting the ability to run complex algorithms and slowing the advancements in quantum computing applications. Reusing qubits by resetting them after measuring and repurposing them for subsequent gate operations offers an effective strategy to reduce the overall qubit requirements. Based on Satisfiability Modulo Theories (SMT) and Integer Linear Programming (ILP), we present an optimal algorithm that maximizes qubit reuse while optionally constraining the circuit depth to a specified upper bound. Our approach considers all feasible circuit rearrangements to enhance optimality, including gate reordering and eager measurement. We further propose a divide-and-conquer approach to scale for large circuits by relaxing the optimality guarantee. Experimental results show that our exact method substantially decreases both the qubit count and the circuit depth compared to the current state of the art, while the divide-and-conquer approach effectively addresses scalability issues with maintained solution quality.
Near-term quantum computations are limited by high error rates, the scarcity of qubits and low qubit connectivity. Increasing support for mid-circuit measurements and qubit reset in near-term quantum computers enables qubit reuse that may yield quantum computations with fewer qubits and lower errors. In this work, we introduce a formal model for qubit reuse optimization that delivers provably optimal solutions with respect to quantum circuit depth, number of qubits, or number of swap gates for the first time. This is in contrast to related work where qubit reuse is used heuristically or optimally but without consideration of the mapping effort. We further investigate reset errors on near-term quantum computers by performing reset error characterization experiments. Using the hereby obtained reset error characterization and calibration data of a near-term quantum computer, we then determine a qubit assignment that is optimal with respect to a given cost function. We define this cost function to include gate errors and decoherence as well as the individual reset error of each qubit. We found the reset fidelity to be state-dependent and to range, depending on the reset qubit, from 67.5% to 100% in a near-term quantum computer. We demonstrate the applicability of the developed method to a number of quantum circuits and show improvements in the number of qubits and swap gate insertions, estimated success probability, and Hellinger fidelity of the investigated quantum circuits.
Recent advances in quantum computing introduce the ability to reuse qubits through mid-circuit measurements, thereby enhancing the efficiency of quantum devices with limited computational resources.However, identifying optimal reuse opportunities in quantum circuits remains challenging due to the intricate dependencies between quantum gates.Existing frameworks address this by either directly searching for reuse opportunities or converting circuits into directed acyclic graphs (DAGs).Unfortunately, these frameworks may require exponential search complexity or may not always ensure optimal results due to their non-deterministic property.To overcome these challenges, we propose QR-Map (Qubit Reuse Map), a map-based framework that abstracts computational dependencies for efficient qubit reuse.By extracting and aligning two-qubit gates, QR-Map facilitates dependency detection and ensures qubit savings without incurring excessive idle time.This approach achieves an optimal balance between gate serialization depth and crosstalk reduction.Evaluations with various quantum circuit benchmarks demonstrate that quantum circuits optimized with QR-Map achieve average reductions of 20% in qubit usage, 25% in circuit depth, and 22% in SWAP insertions compared to those optimized with the state-of-the-art framework.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.